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研究生:王忠暉
研究生(外文):Chung-Huei Wang
論文名稱:適用於同步序列接收器之時序恢復電路設計
論文名稱(外文):A timing recovery circuit for synchronous serial data receivers
指導教授:賴源泰
指導教授(外文):Yen-Tai Lai
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:48
中文關鍵詞:時序恢復
外文關鍵詞:timing recovery
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在此篇論文中我們提出一個適用於高速數位資料傳輸的時序恢復電路,在序列傳輸介面中,時脈信號與資料是混合在一起傳送,故在接收端需設計一時序恢復電路以還原時脈信號。經由結合類比PLL及數位時序恢復電路,輸入信號被取樣並重定時(retime),類比PLL產生一個參考時脈以提供給數位時序恢復電路,此參考時脈頻率為外部時脈頻率的八倍。我們也利用C語言模擬類比低通濾波器的暫態響應,此時序回復電路可操作在480Mb/s的資料速率下
In this thesis a timing recovery circuit designed for a wide range of applications in high-speed serial data communications is presented. By embedding the clock signal into the transmitted data stream, a serial interface can operate at very high data rates without the timing skew problem between the clock and data signals. However, at the receiving end, a clock/data recovery circuit is needed to recover the embedded clock signal from the incoming data stream and to retime the data.
By combining an analog PLL clock synthesizer with a digital clock recovery circuit, it can tolerate long strings of ones and zeros in the incoming data stream since its clocks are generated by the analog PLL which is frequency-locked to a reference clock. The initial phase acquisition can be achieved quickly by sampling the incoming data with multiple clock phases generated by the analog PLL. Also, we have developed a C program to simulate the behavior of the loop filter in the analog PLL. The symbol rate is 240 Mb/s and the equivalent data rate is 480 Mb/s.
Contents
Abstract
Contents
List of Figure
Chapter 1 Introduction……………………………….………….………….1
1.1 Motivation……………………………………………………..…1
1.2 Thesis Organization…………..…………………………...……2
Chapter 2 Timing Recovery Algorithm and Architecture ...…...3
2.1 Introduction…………………………………..…………………..3
2.2 Conventional Timing Recovery……………………………....4
2.2.1 Threshold crossings method…….………………………...5
2.2.2 Spectral-Line Methods…….………………………….…...5
2.2.3 MMSE Method…………………………………………...7
2.3 Timing Extraction Schemes…………………………………..8
2.3.1 Introduction…….…….……………………………………..8
2.3.2 Review of The Timing Recovery Problem...……………… 10
2.3.3 Relating Timing to the Impulse Response………………….12
2.3.4 Extraction of Timing Information………………………….14
2.3.5 A Practical Example………………………………………..15
Chapter 3 Introduction to Phase-Locked Loop………...………….18
3.1 Basic Loop Architecture……………...………………………18
3.2 Linearized Small-Signal Analysis……………..……………24
3.3 Capture Range…………………….……………………………32
Chapter 4 Phase-Locked Loop Circuit Design……..……………..35
4.1 PLL clock generator……………………..……………………35
4.2 PLL Components…………………………………….………..36
4.3 VCO Circuit Design…………..…….…………………………38
Chapter 5 Experimental Results……………………………...………...42
Chapter 6 Conclusions…………………………………………………….47
Reference……………………………………………………………………...…48
[1] W. C. Lindsey and C. M. Chie, “A survey of digital phase-locked loops,”Proc. IEEE, vol. 69, pp. 410–431, Apr. 1981.
[2] M. Bazes and R. Ashuri, “A novel CMOS digital clock and data decoder,” IEEE J. Solid-State Circuits, vol. 27, pp. 1934–1940, Dec. 1992.
[3] B. Kim et al., “A 30-MHz hybrid analog/digital clock recovery circuit in 2-m CMOS,” IEEE J. Solid-State Circuits, vol. 25, pp. 1385–1394, Dec. 1990. µ
[4] J. Sonntag and R. Leonowich, “A monolithic CMOS 10 MHz DPLL for burst-mode data retiming,” in ISSCC Dig. Tech. Papers, 1990, pp.194–195.
[5] B. Guo et al., “A 125 Mbs CMOS all-digital data transceiver using synchronous uniform sampling,” in ISSCC Dig. Tech. Papers, 1994, pp.112–113.
[6] M. Johnson and E. Hudson, “A variable delay line PLL for CPU coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
[7] F. A. Gardner, “Charge pump phase locked loops, ” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
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