跳到主要內容

臺灣博碩士論文加值系統

(54.92.164.9) 您好!臺灣時間:2022/01/23 04:08
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:李偉哲
研究生(外文):Wei-Tse Lee
論文名稱:一個位元平面硬體有效率的可程式化有限脈衝響應濾波器架構
論文名稱(外文):A Bit-Plane Hardware-Efficient Architecture for Programmable FIR Filters
指導教授:何裕琨
指導教授(外文):Yu-Kuen Ho
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:51
中文關鍵詞:位元循序濾波器有限脈衝響應可程式化位元平面
外文關鍵詞:firprogrammablebit-planefilterbit-serial
相關次數:
  • 被引用被引用:1
  • 點閱點閱:216
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:1
由於有限脈衝響應數位濾波器在數位信號處理領域的廣泛應用,擁有高速低成本的有限脈衝響應數位濾波器架構便成為一種強烈的需求,並且也有許多的架構被提出來。在這些眾多架構中,若從位元階層來分,可以分為位元循序(bit-serial),位元平行(bit-parallel),位元組循序(digit-serial)等。其中位元循序的用意,是以時間換取硬體成本,因此適合中低速的應用。位元平行,雖然硬體成本較大,卻很適合高速的應用。位元組循序,則是介於以上兩者之間,適合中等速度的應用。在不同的應用中,需要採用不同的架構,甚至需要發明新的架構以因應。
本論文提出一個架構,在位元階層上,其輸入信號為位元循序,因此在做乘法時,可以簡化乘法為一個選取濾波器係數或零的多工器,使得整個濾波器的運算,變成一些濾波器係數的連加,如此可以大大地減少硬體成本,比起基於基底四布斯(Radix-4 Booth)演算法做乘法的架構,更加節省硬體。此外,利用管線技術以及再排時(Retiming)技術的情形下,可以進一步地減少本架構臨界路徑(critical path)的信號傳遞時間,如此可使本架構達到很高的工作頻率。
本論文所提出的架構,不僅在硬體成本方面節省,也可以在很高的頻率下工作,尤其在濾波器的信號位元數增加,或濾波器長度增加的情形下,仍然保持其優點,所以是一個適用性很廣的架構。
Since FIR filters have a wide variety of applications in the field of digital signal processing, a high-speed low-cost architecture of FIR filters is strongly required and many architectures have been proposed. Among these architectures, they are categorized into bit-serial, bit-parallel, and digit-serial in the level of bits. The intention of bit-serial is to trade time for hardware cost and suitable for medium and low speed applications. Although bit-parallel needs high hardware cost, it is however suitable for high speed applications. Digit-serial owns the property between these two schemes and is fit for medium speed applications. In different cases of applications, we need to adopt different architectures and even need to invent a new architecture to achieve the goal.
This paper proposes an architecture whose input signal is bit-serial in the level of bits. Hence, the operation of multiply is reduced to a mux of selecting fiter coefficients and zeros. This makes the whole operations of the filter become the additions of fiter coefficients, therefore the great reduction of hardware cost. This architecture saves more hardware cost than radix-4 booth based architecture. In addition, we take advantage of retiming to further reduce the propagation delay in the critical path of this architecture. This processing makes our architecture achieve a very high working frequency.
The proposed architecture not only saves hardware cost but also works in a very high working frequency. Especially when the bit number of filter signal or the length of filter increases, this architecture still keeps its strengths. Therefore, the proposed architecture has a wide range of applications.
第一章 緒論 1
第二章 有限脈衝響應濾波器的製作 3
2.1有限脈衝響應濾波器的介紹 3
2.2有限脈衝響應濾波器的實現 8
2.3加法器的架構及種類 12
2.3.1平行加法器(parallel adder) 12
2.3.2進位儲存(Carry-Save )技術 14
2.4乘法器的架構及種類 16
2.4.1平行乘法器(parallel multiplier) 17
2.4.2改良式布斯重編碼(Modified Booth Recoding)技術 19
2.4.3包屋利(Baugh-Wooley)乘法器 20
2.5位元平面處理(BIT PLANE APPROACH) 21
第三章 有限脈衝響應濾波器的工作頻率 24
3.1濾波器的資料流向表示法 24
3.2再排時(RETIMING)轉換技術 26
3.3管線(PIPELINING)技術 31
第四章 位元平面可程式化FIR濾波器架構的設計 34
4.1公式的推導 34
4.2工作頻率的考量 35
4.3完整的架構 37
4.4成本比較 40
第五章 結論 42
參考文獻 43
附錄 46
A.1驗證電路功能的正確性 46
A.2測試電路的執行速度 47
A.3模擬結果 49
[1] Keshab K.Parhi, ”VLSI Digital Signal Processing Systems Design and Implementation,” Wiley-Interscience Publication, 1999.
[2] S. Simon, E. Bernard, M. Sauer, and J. Nossek, “A new retiming algorithm for circuit design,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), (London, England), May 1994.
[3]T. C. Denk and K. K. Parhi, “Two-dimensional retiming”, IEEE Trans. on VLSI Systems, vol. 7, 1999.
[4]Neil H. E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI Design: A Systems Perspective,” Addison Wesley, 1992.
[5]Miroslav D. Lutovac, Dejan V. Tosic, Brian L. Evans, “Filter Design for Signal Processing Using Matlab and Mathematica,” Prentice Hall, 2001.
[6]M. Sid-Ahmed, “A systolic realization for 2-D digital filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 560-565, Apr. 1989.
[7]D. Reuver and H. Klar, “A configurable convolution chip with programmable coefficients,” IEEE J. Solid-State Circuits, vol. 27, pp. 1121-1123, July 1992.
[8]T. Noll, “Carry-save arithmetic for high-speed digital signal processing,”J. VLSI Signal Processing, vol. 3,pp. 121-140,1991.
[9]Bruce Edwards, Alan Corry, Neil Weste, and Craig Greenberg , “A single chip video ghost canceller”, Proceedings of the IEEE 1992, Custom Integrated Circuits Conference, pp. 26.5.1-26.5.4, May 1992.
[10]Hwan-Rei Lee, Chein-Wei Jen, and Chi-Min Liu, “A new hardware-efficient architecture for programmable FIR filters”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.43, Issue 9, pp. 637 -644, September 1996.
[11]Li-Hsun Chen, Oscal T.-C. Chen, “A low-complexity and high-speed booth-algorithm FIR architecture”, The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001., vol. 4 , pp. 338 -341 ,2001.
[12]連國珍 , “數位信號處理簡介”,茂昌,民國84
[13]蒙以正 , “以MATLAB透視DSP”,�眳p,1999
[14]蕭如宣 , “VHDL數位系統電路設計”,儒林,2000
[15] 教育部教職進修網站, http://dsptec.ee.ntou.edu.tw/
[16]H. Samueli, “An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients,” IEEE Trans. Circuits and Syst., vol. 36, pp. 1044-1047, July 1989.
[17]S. A. White, “Applications of distributed arithmetic to digital signal processing : A tutorial review,“ in IEEE Asia-Pacific Conf. Circuits Syst., pp. 4-18,July 1989.
[18]H. –R. Lee, C. –W. Jen, and C.-M. Liu,”On the design automation of the memory-based VLSI architectures for FIR filters,” IEEE Trans. Consumer Electron., pp. 619-630, Aug. 1993.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top