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研究生:許浚偉
研究生(外文):Chun-Wei Hsu
論文名稱:一個具有新設計技術之六位元快閃式類比/數位轉換器
論文名稱(外文):A 6-Bit Flash A/D Converter with New Design Techniques
指導教授:郭泰豪
指導教授(外文):Tai-Haur Kuo
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:114
中文關鍵詞:快閃式類比/數位轉換器
外文關鍵詞:flash ADC
相關次數:
  • 被引用被引用:1
  • 點閱點閱:282
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  • 下載下載:85
  • 收藏至我的研究室書目清單書目收藏:1
本篇論文提出一個具有新設計技術之高速六位元互補金氧半快閃式類比數位轉換器。對於連續信號轉換的應用,
無空轉時間之自動歸零技術是最有效的方法來壓抑由於製程變動所產生的誤差。
內插技術則可以有效降低輸入負載與前置放大器數目。
然而,要同時將無空轉時間之自動歸零與內插操作實現於一高速低潛伏的快閃式類比數位轉換器是相當困難的。
在本設計中,新的自動歸零與內插(NAI)技術被提出來實現這個目標。
一開關式前置放大器被提出於NAI技術中來避免傳統自動歸零所需之需要非重疊控制信號與消除高速自動歸零對輸入端造成的干擾。
除此之外,相對於最近發表的具自動歸零之快閃式類比數位轉換器所須多相位時脈,NAI有單一相位控制的優點並避免了同步問題。

由於在NAI技術裡,電荷注入與貫穿效應會限制了類比數位轉換器性能,因此利用電容平均技術結合於NAI技術來減低這些誤差。因為在內插方法的使用上,需要大內插阻抗來產生足夠的內插信號以克服雜訊跟偏移誤差。
而這在內插點會造成大的RC時間常數且使ADC操作速度下降。
負阻抗補償技術被提出來解決這個問題使類比數位轉換器可以有小RC時間常數而達到較高的轉換速率。

所設計的類比數位轉換器是實現於0.25μm 1P5M互補金氧半製程,面積為1.0x0.8 mm^2。
量測結果顯示此設計可以達到500MHz的操作速度並有大於30分貝的信號雜訊比,而整個晶片在2.5V的供應電壓下,消耗了261mW的功率。
The thesis presents a high-speed 6-bit CMOS flash ADC
with new design techniques. Autozeroing technique without idle time is the most effective way to
suppress the errors due to process variation for the applications of continuous input conversion.
Interpolation technique can reduce the input loading and the preamplifiers' number efficiently.
However, it is difficult to include autozeroing without idle time and interpolation operations in
a high-speed low-latency flash ADC at the same time.
In this design, New Autozeroing with Interpolation (NAI) technique is proposed
to achieve the target.
A switching preamplifier is provided in NAI to
avoid using non-overlap control signals required by the conventional autozeroing ADCs and to
eliminate the
interference, caused by the high-speed autozeroing operation, at input nodes.
Besides, NAI has the merit of a single-phase control to avoid
the synchronous problem since the multi-phase clocks are
necessary for recent published flash ADCs with autozero.

While charge injection and feedthrough in NAI
limit the ADC performance, capacitor averaging technique is incorporated
with NAI to decrease these errors.
For the use of interpolation approach, large impedance is needed to generate enough
interpolation signals to overcome noise and offset errors. That causes
a large RC time constant at the interpolation nodes and deteriorates the ADC speed.
A technique called, Negative Impedance Compensation (NIC),
is presented to solve this problem so that the ADC
can thereby achieve a higher conversion rate with small RC time constant.

The designed ADC is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.0x0.8 mm^2. The measurement results show that the design can achieve an
operating rate of 500MHz with a SNR>30dB.
The total chip draws 261mW from 2.5V power supply.
Introduction 1
1.1 Motivation1
1.2 ThsisOrganization2
2 Overview ofHigh-Speed ADC 3
2.1 Introduction3
2.2 FlashA/DConvrtr3
2.3 Two-step Subrange A/D Conv rter 5
2.4 FoldingA/DConvrtr 7
2.5 PipelindA/DConvrtr 9
2.6 IntrlavdTopology 10
2.7 6-bitA/DConvrtrArchitctur 13
3 Error Analysis of6b Flash ADC 14
3.1 Quantization 14
3.2 Metastability and Hysteresis 22
3.3 ClockSkwE ct 24
3.4 ComparatorDlayError 27
3.5 Apertur Jittr 30
3.6 Nois 35
3.7 O stMismatch 39
4 Proposed Techniques for the ash ADC 43
4.1 AutozroingTchniqu 43
4.1.1 AutozroingPrincipl 44
4.1.2 AutozroingTopology 45
4.1.3 Modi fidAutozroing 47
4.2 AvragingTchniqu 50
4.2.1 AvragingTratmnts 51
4.2.2 AvragingImplmntationAnalysis 53
4.3 IntrpolationTchniqu 58
4.3.1 IntrpolationTypes 59
4.3.2 IntrpolationAnalysis 61
4.4 NwAuto-zroingwithIntrpolation 64
4.5 CapacitorAvraging 72
4.6 NgativImpedanc Compensation 78
5 Circuit Design ofthe Flash ADC 83
5.1 ThArchitctur ofProposdADC 83
5.2 ComparatorCircuitDsign 84
5.2.1 CircuitTopologyandConsidrations 84
5.2.2 InputStag ofComparator 85
5.2.3 Prampli firsandNICCircuit 89
5.2.4 LatchCircuits 90
5.3 Rfrnc LaddrConsidrations 91
5.4 DigitalEncodrDsign 94
5.4.1 ConsidrationsofEncodr 95
5.4.2 ImplmntationofEncodr 96
5.5 TimingGnratorCircuit 97
6 LayoutandResults 99
6.1 FloorPlanandLayoutConsidrations 99
6.2 SimulationRsults 101
6.3 MasurmntIssus 103
6.3.1 MasurmntStp 104
6.3.2 PCBFabrication 104
6.4 ExperimntalRsults105
7 Conclusions and Future Work 109
References 114
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