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研究生:林偉中
研究生(外文):Wei-Zhong Lin
論文名稱:具有時脈管理系統的AMBA相容10/100/1000Mbps乙太網路媒介存取控制晶片之研製
論文名稱(外文):10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System
指導教授:陳中和陳中和引用關係
指導教授(外文):Chung-Ho Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:96
中文關鍵詞:時脈管理乙太網路媒介存取控制晶片極大形積體電路晶片設計
外文關鍵詞:MACARMAMBAEthernetMIIGMII
相關次數:
  • 被引用被引用:0
  • 點閱點閱:355
  • 評分評分:
  • 下載下載:92
  • 收藏至我的研究室書目清單書目收藏:2
摘要

在本篇論文我們設計並實作出一個具有時脈管理系統的AMBA相容10/100/ 1000 Mbps 乙太網路媒介存取控制晶片。在本晶片與Host system的溝通介面部分,提供了與AMBA Bus system相容的匯流排介面。在對於實體層的溝通方面,則是提供同時支援MII (for 10/100 Mbps transmission speed)以及GMII(for 1000 transmission speed)兩種不同的媒體介面。我們內建了一個能夠減少能源消耗的時脈管理系統(Clock management system),時脈管理系統能依照目前的工作情形對於時脈的輸入進行管理,可以減少能源在時脈上無謂的消耗。
晶片的工作方式是依照來自於上層的要求作傳送封包的動作,透過AMBA中的資料匯流排取得要傳送的封包資料,加上CRC檢查碼後,經由MII傳送到實體層。MAC同時會監聽來自於實體層的訊息,如果有封包資料傳來,會把資料從實體層接收進來暫存在Buffer中,在經過Destination Address以CRC碼檢查無誤後,將封包資料上傳到AMBA匯流排上。在工作過程中,時脈管理系統會同時動作,進行時脈管理以達到省電的目的。
我們的Tri-speed MAC是以Verilog HDL RTL程式撰寫。並且以“Xilinx foundation series F3.1i ”實作。在驗證方面,我們提供了一個完整的MAC研發測試環境,包括Modelsim Function simulation的驗證環境以及FPGA驗證環境,並且在上述的環境中驗證成功。
Abstract

This thesis presents the design and implementation a 10/100/1000 tri-speed MAC with low power consumption for AMBA (Advanced Microcontroller bus architecture) system chip that complies with IEEE 802.3z standard. We provide AHB interface of the AMBA bus system as the communication channel between the tri-speed MAC and the host system, and a two-in-one interface of GMII and MII for physical layer devices. We have also developed a clock management module to reduce power consumption. This MAC chip achieves the goal of reducing the power consumption by controlling the clocks.

When our Tri-speed MAC works on transmission, a valid frame data from the LLC is striped and converted into a string of serial data and passed to the PHY. On receiving, the chip aggregates the serial data via Gigabit Media Independent Interface (GMII) from the Physical Layer and passes a valid frame to the Logical Link Control Layer (LLC).

The Tri-speed MAC unit is implemented in RTL codes using Verilog HDL. We implement the Tri-speed MAC with “Xilinx foundation series F3.1i”. We also provide the ModelSim function simulation environment and the FPGA simulation environment. The design is verified in ModelSim function simulation environment and an FPGA board with physical layer protocol for Ethernet compatibility.
目錄
Chapter1. 序論 1
1.1 研究動機 1
1.2 研究方向 1
1.3 研究貢獻 2
1.4 章節介紹 2
Chapter2. Tri-speed MAC的設計 3
2.1 Receive MAC 4
2.1.1 Receiver 4
2.1.2 CRC checker 4
2.1.3 Rx AHB bus interface 4
2.2 Transmit MAC 5
2.2.1 Transmitter 5
2.2.2 CRC generator 5
2.2.3 Tx AHB bus interface 5
2.3 控制模組 5
2.3.1 Receive DMA controller 6
2.3.2 receive FIFO controller 8
2.3.3 Transmit DMA controller 10
2.3.4 Transmit FIFO controller 13
2.4 Transmit FIFO以及Receive FIFO 15
2.5 AHB (AMBA advanced High-performance Bus)介面簡介 17
2.5.1 AMBA匯流排系統簡介 17
2.5.2 AHB介面簡介 18
2.6 GMII /MII compatible interface 簡介 20
Chapter3. Clock Management 23
3.1 MAC各個模組的分類 23
3.2 Clock manage的工作原理 25
3.3 Clock management work mode 26
3.3.1 Clock manage basic mode 27
3.3.2 Clock management mode 28
3.4 Clock manager的省電效能評估 32
Chapter4. Tri-speed MAC的工作環境以及工作方式 34
4.1 Frame format 34
4.2 MAC的工作環境 35
4.3 MAC的工作方式 36
4.3.1 Receive mode 36
4.3.2 Transmit mode 36
4.3.3 Flow control 39
4.3.4 二元指數後退演算法 40
4.3.5 載波延伸(Carrier Extension) 41
4.3.6訊框爆發模式(Frame Bursting mode) 41
Chapter5. 功能驗證 43
5.1 接收功能驗證 44
5.1.1 AHB介面功能驗證 44
5.1.2 在半雙工模式下接收10/100 Mbps封包 45
5.1.3 在半雙工模式下接收1000 Mbps封包 47
5.1.4 在半雙工模式下接收控制封包(Control frame : Pause) 49
5.1.5在半雙工模式下接收目的地位址錯誤的封包 50
5.1.6在半雙工模式下接收CRC檢查碼錯誤的封包 51
5.1.7 在半雙工模式下接收CRC欄位錯誤的Broadcast 封包 52
5.2 傳送功能驗證 54
5.2.1 AHB介面功能驗證 54
5.2.2 在半雙工模式下傳送單一10/100 Mbps封包 55
5.2.3在半雙工模式下傳送單一1000 Mbps封包(Gigabit Carrier Extension) 56
5.2.4 在Gigabit 訊框爆發半雙工模式下傳送多筆封包 59
5.2.5 傳送封包時發生碰撞 61
5.3 FPGA及實體層測試 65
5.3.1 FPGA建立測試環境 65
5.3.2 FPGA初始化 66
5.3.3 Tri-speed MAC的FPGA驗證。 67
5.4 實作成果報告 70
Chapter6.Conclusion 74
References 75
Appendix A : Tri-speed MAC Register set 77
A.1 Frame Descriptor 77
A.1.1 Frame Descriptor data structure 77
A.1.2 RX Descriptor Format 78
A.1.3 TX Descriptor Format 79
A.2 MCR:MAC Control Register (00h) 80
A.3 MBCR:MAC Bus Control Register (04h) 81
A.4 MICR:Interrupt Control Register (08h) 82
A.5 MTPR:TX Poll Command _Register (0Ch) 83
A.6 MRBSDCR:RX Buffer Size and Descriptor Control Register (10h) 84
A.7 MLSR:MAC Last Status Register(14h) 84
A.8 MDIO:Control Register (18h) 85
A.9 MDIO:Status Register (1Ch) 87
A.10 MDIO:Extended Status Register (20h) 89
A.11 MTDSA:TX Descriptor Start Address (24h) 90
A.12 MRDSA:RX Descriptor Start Address (28h) 91
A.13 MISER:INT Status and Enable Register(2Ch) 92
A.14 MECISER:Event Counter INT Status and Enable Register (30h) 93
A.15 MRTCNT:Successfully Received and Transmit Packet Counter (34h) 94
A.16 MECNT1:Event Counter 1 (38h) 94
A.17 MECNT2:Event Counter 2 (3Ch) 95
A.18 MCENT3:Event Counter 3 (40h) 95
References
[1] AMBA specification (Rev 2.0).
[2] ARM940T (Rev 1) Technical Reference Manual.
[3] ARM Target Development System User Guide.
[4] A. S. Tanenbaum, “Computer Networks,” 3rd, Prentice-Hall, INC.,1996.
[5] Broadcom silicon solution for broad band communications Home Page
URL: http://www.broadcom.com/
[6] C. H. Chen, M. H. Sheu, M. D. Shieh, T. S. Li, and M. C. Chen, “Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,” Proceeding of the IEEE Asia Pacific Conference on Communications, 1998.
[7] Gigabit Ethernet References Home Page
URL:http://www.cis.ohiostate.edu/~jain/refs/gbe_refs.htm#GB_Ether
[8] Gigabit Ethernet Alliance Home Page
URL: http://www.gigabit-ethernet.org/
[9] H. Ahmadi and W. E. Denzel, “A survey of modern high-performance switching techniques,” IEEE Joural on Selected Areas in Communications, vol.7, No.7, September 1989.
[10] IEEE Std.802.3, 1998 Edition.
[11] IEEE P802.3z Gigabit Task Force Home Page
URL:http://grouper.ieee.org/groups/802/3/z/index.html
[12] IEEE 802.3 CSMA/CD (ETHERNET) Home Page
URL: http://grouper.ieee.org/groups/802/3/index.html
[13] Jing-Fei Ren and R Landry, “Flow Control and Congestion Avoidance in Switched Ethernet LANs,” IEEE International Conference, Vol.1, 1997.
[14] J. Kadambi, M. Kalkunte, and I. Crayford, “GIGABIT ETHERNET—Migrating to High-Bandwidth LANs,” Prentice-Hall, INC., 1998.
[15] K. J. Christensen, M. Molle, and Sifang Li, “Comparison of the Gigabit Ethernet Full-Duplex Repeater, CSMA/CD, and 1000/100 –Mbps Switched Ethernet,” LCN’98 Proceedings, 23rd Annual Conference , 1998.
[16] Lucent Technologies, “LU5M31 Gigabit Ethernet Media Access Controller (MAC),” Advance Data Sheet, August 1998.
[17] M. Molle, M. Kalkunte, and J. Kadambi, “Frame Bursting: A Technique for Scaling CSMA/CD to Gigabit Speeds,” IEEE Network, Vol.114, July-Aug. 1997.
[18] M. H. Shue, C. H. Chen, M. D. Shieh, and T. S. Li, “A High Performance VLSI Architecture Design for 10/100 Mbps Ethernet Switching Fabric,” Digest of Technical Papers, 1998.
[19] Ming-chih Chen and Chung-Ho Chen, ” Implemen-tation and Performance Evaluation of a 10/100 Mbps Ethernet Switching Hub Controller,” Dept. of Electronics and Information, National Yunlin University, February 1999.
[20] M. C. Chen, I. J. Huang, and C. H. Chen, “Parameter MAC Unit Implementation,” Design Automation Conference, 2001.
[21] M. D. Shieh, M. H. Shue, C. H. Chen, and H. F. Lo, “A systematic Approach for Parallel CRC Computations,” Journal of Information Science and Engineering, Vol.17, pp. 445-461, 2001.
[22] R. Seifert, “Gigabit Ethernet: technology and application for high speed LANs,” Prentice-Hall, INC., 1997.
[23] R. Breyer and S. Riley, “Switched, Fast, and Gigabit Ethernet,” 3rd, Macmillan Technical Publishing, 1999.
[24] S. Sathaye, K. K. Ramakrishnan, and H. Yang, “FIFO design for a high-speed network interface.” IEEE Local Computer Networks, 1994.
[25] Samsung Electronics, “KS32C50100 High Performance Network Controller,” Users Manual, Feb. 2000.
[26] Switched Ethernet Controller, GT-48001 Rev.1.1, Galileo Technology, December 19, 1996.
[27] Shu-Hung Li, ”Design and Implemen-tation of Gigabit Ethernet Media Access Control Chip,” Dept. of Electrical Engineering, National Chen-Kung University,July 2001.
[28] T. B. Pei and C. Zukowski, “High-Speed Parallel CRC Circuits in VLSI,” IEEE Transactions on vol.404, April, pp. 653-657, 1992.
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