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研究生:吳光立
研究生(外文):Kuang-Li Wu
論文名稱:單晶片整合之匯流排轉換器設計方法論
論文名稱(外文):Bus Wrapper Design Methodology in SoC
指導教授:周哲民
指導教授(外文):Jer-Min Jou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:92
中文關鍵詞:介面協定轉換系統單晶片匯流排轉換器
外文關鍵詞:VCIPCIAHBinterface protocolSoCbus wrapper
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單晶片整合之匯流排轉換器設計方法論
吳光立* 周哲民**
國立成功大學電機工程研究所
摘 要
在本論文中,我們提出一個匯流排轉換器的設計方法,以作為產生與合成介面電路的系統設計模型。這一個設計方式可以應用於以匯流排為基礎的系統單晶片整合上。在整合IP的課題之下,首先,設計現今最流行的AMBA High Performance Bus (On-Chip-Bus) 與標準介面(Virtual Component Interface)的轉換器,再者是電腦系統中最通用的PCI Bus (On-Board-Bus) 與標準介面的轉換器。並利用以上的設計經驗,整理出設計一個匯流排轉換器的方式與步驟。我們可以利用AHB匯流排轉換器,將具有標準介面的IP整合到ARM發展系統當中。亦可以利用PCI匯流排轉換器,將具有標準介面的IP整合到個人電腦系統當中。
主要的設計考量為面積的考量,因此設計的時候,並不使用FIFO做為資料與位址的暫存空間,而是利用幾個緩衝器做為設計準則,因為在系統單晶片中的IP有一定的數量,如果轉換器的面積太大,會造成很大的影響。再來是做效能的考量,主要的設計方式為Mealy Machine的方式設計,使的輸入端的訊號能盡快的在輸出端輸出,以減少轉換器所造成的延遲(Latency)。
* 作者
** 指導教授
Bus Wrapper Design Methodology in SoC
Kuang-Li Wu* Jer-Min Jou**
Department of Electrical Engineering
National Cheng Kung University
Tainan, Taiwan, Republic of China
ABSTRACT
In this paper, the bus wrapper design methodology is proposed in order to generate and synthesize communication interfaces in a system design context. This methodology will be used in bus-based SoCs for IP integration. To verify the practicability, we use this methodology to implementation the on-chip bus wrapper and on-board bus wrapper based on Virtual Component Interface (VCI)-compliant IPs by three cases, which are the AHB master wrapper, the AHB slave wrapper, and the PCI bus target wrapper. We can use the AHB wrapper to integrate the VCI-compliant IP into ARM development system, or use PCI wrapper to integrate the VCI-compliant IP into personal computer system.
In the bus wrapper design we use the buffer to store the address and data temporary instant of FIFO, so we only use a small amount the area of bus wrapper. At the performance of the bus wrapper, we use the Mealy Machine Design method, so the input and output of the interface can be pass through the wrapper as soon as possible. It will not cause the communication latency between the interface of the bus and standard interface.
*The author
** The advisor
Abstract Chinese
Abstract English
Content
List of figures
List of tables
Chapter 1 INTRODUCTION
1-1 Why we use IP (Intellectual Property)? …………………………………………2
1-2 Successful design for IP reuse……………………………………………………3
1-3 How can the IP have portability?…………………………………………………3
1-4 Compare with the ASIC design flow and IP-based IC design flow………………4
1-5 Paper organization…………………………………………………………………6
Chapter 2 Virtual Component Interface of VSIA
2-1 Peripheral Virtual Component Interface…………………………………………8
2-1-1 Signal Definitions………………………………………………………………9
2-1-2 PVCI operation types…………………………………………………………..10
2-2 Basic Virtual Component Interface………………………………………………11
2-2-1 Definitions of Transfer Units……………………………………………………11
2-2-2 Signal Definitions………………………………………………………….…..12
2-2-3 BVCI handshake rules…………………………………………………………14
2-2-4 BVCI operation types………………………………………………………….14
2-3 Advanced Virtual Component Interface…………………………………..……...15
2-3-1 Signal Definitions……………………………………………………………...16
2-3-2 AVCI operation types……………………………..……………………………18
Chapter 3 ARM High Performance Bus
3-1 Bus interconnection………………………………………………….…………..21
3-2 Basic Transfer of AHB…………………………………………………………...21
3-3 Burst Operation of AHB…………………………………………..……………..22
3-4 Address Decoder………………………………………………..………………..23
3-5 Signal Definitions………………………………………………………………..24
3-6 Operation types…………………………………………………………………..26
3-7 The interface of the AHB bus………………………………………………..…..28
3-7-1 AHB bus slave…………………………………………………………..……28
3-7-2 AHB bus master………………………………………………………………..28
3-7-3 AHB bus arbiter………………………………………………………………..28
Chapter 4 Peripheral Component Interconnect Bus
4-1 Configuration register……………………………………………………………31
4-2 Signals Definitions……………………………………………...………………..35
4-3 Basic Transfer of PCI Bus………………………………………………………..36
Chapter 5 Interface Protocol Conversion Methodology
5-1 Interface Generation……………………………………………………………...38
5-2 Bus Wrapper Design Models…………………………………………………….43
Chapter 6 Bus Wrapper between VCI and AHB
6-1 AHB Bus Master Wrapper……………………………………………………….46
6-1-1 AHB Bus Master State Machines………………………………..…………….46
6-1-2 Finite State Machine of the Bus Wrapper…………………………….………..47
6-1-3 Burst Controller…………………………………….………………………….51
6-1-4 Address decoder and the data path………………………………...……...……52
6-1-5 the BVCI/AHB Master bus wrapper architecture………………………...……53
6-1-6 simulation result…………………………………………………………..…...55
6-2 AHB Bus Slave Wrapper…………………………………………………………60
6-2-1 AHB Bus Slave State Machines……………………………………..………...60
6-2-2 Finite State Machine of the Bus Wrapper……………………………...………61
6-2-3 Burst Controller………………………………………………...……………...63
6-2-4 Address decoder and the data path…………………………………..…………64
6-2-5 the BVCI/AHB Master bus wrapper architecture……………………...………65
6-2-6 simulation result…………………………………………………..…………...66
Chapter 7 Bus Wrapper between VCI and PCI
7-1 PCI Bus Target Wrapper……………………………………………...………….72
7-1-1 PCI Bus Target State Machines………………………………….…………….72
7-1-2 Finite State Machine of the Bus Wrapper……………………………….……..73
7-1-3 Configuration Register……………………………………………..………….75
7-1-4 Address decoder and the data path……………………………………………..77
7-1-5 the BVCI/PCI Target bus wrapper architecture……………………….……….78
7-1-6 simulation result……………………………………………………………….79
Chapter 8 APPLICATION
8-1 IEEE 1394 Card with the PCI bus interface……………………………….……84
8-1-1 Simulation of the IEEE 1394 FIFO……………………………………………86
8-2 Multimedia on ARM Develop System…………………….……………………88
Chapter 9 CONCLUSION
Reference…………………………………………………………………………..91
[1]J. A. Rowson and A. Sangiovanni-Vincenteli. “Interface based design”, in Proc. Of the 35th DAC 1998.
[2]J. Rozenblit and K. Buchenrieder, editors. “Codesign : Computer-Aided Software/Hardware Engineering”, chapter Introduction, pp3 – 10. IEEE Press, 1995.
[3]J. L. Huang, M. K. Iyer and K. T. Cheng, “A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs", IEEE VLSI Test Symp, 2001.
[4]A. Rajawat, M. Balakrishnan, A. Kumar, “Interface synthesis: issues and approaches,” VLSI Design, 2000. 13th International conference on, 2000, pp. 92-97
[5]Jer-Ming Jou, Hsiao-Cheng Wang “Methodology of Hierarchical Interface Design and Modeling-A Case study of MPEG 2 Video Decoding” Department of Electrical Engineering NCKU, Tainan, Taiwan, R.O.C June, 2000.
[6]Jer-Ming Jou, Kuang-Ming Wu “Research and Development of a Hierarchical Interface Design methodology and models for SoC IP Integration – Using MP3 design as a case” Department of Electrical Engineering NCKU, Tainan, Taiwan, R.O.C June, 2001.
[7]C. K. Lennard, P. Schaumont, G. de Jong, A. Haverinen, and P. Hardee, “Standards for system-level design: practical reality or solution in search of a question ?” in Proc. Design Automation and Test in Europe, Mar. 2000
[8]On-Chip Bus Development Working Group. “Virtual Component Interface Standard Version 2”, April 2001.
[9]Geneviève Cyr, Guy Bois, Mostapha Aboulhamid, Jacques Baillairgé. “Synthesis of communication interfaces using VSIA recommendations” Proc. of DATE 2001, Munich, Allemagne/Germany, 03/2001.
[10]“AMBATM Specification Revision 2.0”, May 13,1999.
[11]“Advanced High Performance Bus Controller (AHBC)” by Tality Corporation 2001.
[12]“PCI system architecture fourth edition” by MindShare Inc., Tom Shanley and Don Anderson.
[13]PCI Special Interest Group, “PCI Local Bus Specification Revision 2.2” December 18, 1998.
[14]J. D. Kleinsmith and D. D. Gajski, “Communication Synthesis for Reuse”, Technical Report ICS 98-06, University of California, Irvine, February 1998.
[15]S. Narayan, D.D. Gajski. “Interfacing System Components by Generation of Interface Processes.” Proceedings of the 32nd Design Automation Conference. June 1995.
[16]G. Borriello, R.H. Katz. “Synthesis and Optimization of Interface Transducer Logic” Proceedings of the International Conference on Computer-Aided Design. 1987.
[17]J. Akella and K. L. McMillan, "Synthesizing Converters Between Finite State Protocols", IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, 14-16 Oct. 1991, pp. 410-13.
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