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研究生(外文):Ning-Yaun Ker
論文名稱(外文):A Low-Power SDRAM Controller on an8-bit RISC CPU
指導教授(外文):Chung-Ho Chen
外文關鍵詞:close page policyopen page policylow powerSDRAM
  • 被引用被引用:5
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因為無線系統和行動式電腦的蓬勃發展,使得能源管裡的對硬體設計的影響越來越深。在嵌入式系統之中,記憶體晶片佔去了很大一部份的電能消耗。於是在很多的論文之中有許多的新架構被發表出來,這些架構可以減少記憶體讀取的延遲和降低記憶體對能源的消耗。在這篇論文裡,我們探討一個運用在SDRAM 能源模式的管理方式於記憶體控制器上。這個管理方式的核心,是使用一個匯流排使用率的監控器於SDRAM 控制器上,管理SDRAM 晶片的動作。這個方法可以降低能源的消耗,其原理是於匯流排使用率降低的時候,動態的使SDRAM 記憶體進入低能源模式;在匯流排使用率較高時,使用open page 的模式管理記憶體,以節省能源和執行時間。我們使用匯流排使用率監控的方式,可以降低記憶體能源達26 個百分比,而且不會增加記憶體額外的執行時間。
The fast growth of mobile computing and pocket computer has increased the effect of energy management in hardware design greatly. Memory chips occupies a great part of power consumption in an embedded system. There are several architectural approaches to improve SDRAM access latency and to reduce power consumption. In this thesis we present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively
switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization monitor predictor reduces memory energy consumption by 26% without the expense of increasing program execution time.
摘要 I
Abstract II
誌謝 III
圖目錄 E
Chapter 1. 序論1
1.1. 研究動機1
1.2. 研究方向1
1.3. 研究貢獻1
1.4. 內容的編排1
Chapter 2. 背景知識之介紹3
2.1. SDRAM 的介紹3
2.1.1. SDRAM 的簡介3
2.1.2. 記憶體的結構4
2.1.3. SDRAM 的接腳6
2.1.4. 如何對記憶體作存取6
2.1.5. Electrical characteristics9
2.1.6. 記憶體各個狀態的耗電量10
2.1.7. SDRAM module 的Control register 11
2.2. SDRAM controller 對記憶體的Bank active or inactive 的管理方式11
2.2.1. SDRAM Operation12
2.2.2. Close Page Policy14
2.2.3. Open Page Policy 15
2.3. SDRAM controller 對記憶體省電模式的管理方式16
2.3.1. 省電模式控制的概論17
2.3.2. 一些常用的省電模式Predictor 20
Chapter 3. SDRAM controller 的設計與方法27
3.1. SDRAM controller 所連接的Host bus 的類型27
3.1.1. 用AMBA bus 所設計的SDRAM controller27
3.1.2. 在與CPU 整合的階段,配合CPU 的架構改為使用CPU 的Local
3.2. SDRAM controller 從host bus 接收訊號的處理35
3.3. SDRAM controller 支援Open page policy and close page policy 的硬體設
3.3.1. 實作close page policy 38
3.3.2. 實做Open Page Policy 38
3.4. SDRAM controller Finite State Machine 的設計40
3.4.1. SDRAM Initialization Using Finite State Machine 40
3.4.2. SDRAM Refresh Using Finite State Machine 41
3.4.3. SDRAM read/write Using Finite State Machine42
3.5. Bus Utilization Monitor Policy Threshold Predictor 43
Chapter 4. 系統效能測試45
4.1. 基本功能測試45
4.1.1. Initialize and Load Mode Register 45
4.1.2. Auto Refresh 46
4.1.3. Read operation with a hit 46
4.1.4. Read operation with a miss 47
4.1.5. Power down48
4.2. The Performance of SDRAM Power Mode control testing by random
address and random length access48
4.2.1. 測試規格49
4.2.2. 測試結果49
4.2.3. 數據分析與討論54
4.3. Open Page Policy VS Close Page Policy 55
4.3.1. 測試平台的規格55
4.3.2. 測試程式56
4.3.3. 測試結果和數據59
4.4. The performance of SDRAM Controller Using Bus Utilization Monitor
Scheme 65
4.4.1. 實驗程式65
4.4.2. 實驗結果66
Chapter 5. 結論71
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