跳到主要內容

臺灣博碩士論文加值系統

(3.87.33.97) 您好!臺灣時間:2022/01/27 16:47
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:許哲綸
研究生(外文):Jer-Lun Hsu
論文名稱:鎖相迴路之內建時脈抖動量測方法
論文名稱(外文):An On-Chip Method for PLL jitter Measurement
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:51
中文關鍵詞:鎖相迴路時脈抖動量測
外文關鍵詞:PLLJitter Measurment
相關次數:
  • 被引用被引用:0
  • 點閱點閱:473
  • 評分評分:
  • 下載下載:97
  • 收藏至我的研究室書目清單書目收藏:1
在單晶片或混合訊號系統中,鎖相迴路電路為一個重要的建構單元。鎖相迴路的應用很多如:去除時脈偏斜、降低時脈抖動,頻率合成與時脈資料回復等等。但隨著鎖相迴路應用的快速成長,設計複雜度的增加,鎖相迴路的測試變得相當困難,值得去重視。
對於鎖相迴路而言,時脈抖動是一個重要的參數,時脈抖動定義為正確時脈轉換時間點的誤差。在量測時脈抖動時,通常需要昂貴的測試儀器,所以本論文提出一個簡單的架構來偵測時脈抖動。在有時脈抖抖動發生時的狀況紀錄在一錯誤計數器中。之後,並得到一個錯誤次數的累積統計圖,經由分析此統計圖即可求得時脈抖動方均根值。本測試電路並沒有連接到鎖相迴路中易受影響的節點,所以並不會對電路效能有所影響 。
此外,我們亦設計操作範圍在600~900MHz的鎖相迴路,採用TSMC 0.35um的製程技術實現,以便和測試電路整合,達到內建自我測試的目標
In an SOC or a mixed-mode system, a phase-locked loop (PLL) is an important building block which provides many useful applications such as skew suppression, jitter reduction, frequency synthesizing, and clock and data recovery. With the variety of PLL applications and the increase of the design complexity, the testing of PLL has become a critical problem in SOC testing.
Jitter is a key parameter of a PLL and is defined as the deviation from the precise clock transition. Conventionally it needs an expensive Automatic Test Equipment (ATE) for jitter measurement. In this thesis, we propose a simple on-chip architecture to detect this timing error. If a timing error occurs, it is recorded in an error counter. Then a statistical chart of the error count can be plotted and the root-mean-square (RMS) value of the jitter can be obtained by analyzing the statistical chart. In our design, the test circuits do not access the sensitive nodes in the PLL circuit and will have minimum impact on the PLL performance.
We implement a PLL in order to integrate it with our test architecture and to verify our testable design the purpose of BIST. The range of the operating frequency of the PLL is 600~900MHz. The PLL is implemented using the TSMC 0.35um1P4M technology.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of Thesis
Chapter 2 Background and Previous Work 4
2.1 Background 4
2.1.1 The Basic Architecture and Linear model for PLL 4
2.1.2 Charge-Pump PLL 7
2.1.3 Third-Order PLL 8
2.1.4 PLL Applications 10
2.2 Previous Work on PLL testing 12
2.2.1 Structural Test 13
2.2.2 Functional Test 14
2.2.3 Comparison 15
Chapter 3 An implement of Frequency Synthesizr 18
3.1 Overview 18
3.2 Phase Frequency Detector 19
3.3 Charge Pump and Loop Filter 21
3.4 Voltage-Controlled Oscillator 25
3.4.1 Introduction 25
3.4.2 The Characteristic of Adopted Circuit 28
3.5 Frequency Divider 30
3.6 Simulation Results and Layout 33
Chapter 4 A Proposed Architecture for Jitter Measurement 35
4.1 A BIST for PLL 36
4.1.1 Jitter Measurement for PLL 36
4.1.2 Setup Time and Hold Time Violations 39
4.2 Jitter Arbiter 41
4.3 Phase Blender 44
4.4 The Proposed Architecture of Jitter
measurement 46
Chapter 5 Conclusions and Future Work 48
5.1 Conclusions 48
5.2 Future Work 49
[1] A. Hajimiri, T. H. Lee, “The Design of Low Noise Oscillators,” Kluwer Academic Publishers, 1999.
[2] B. Razavi, “Monolithic phase-locked loops and clock recovery circuits,” IEEE Press, New York, USA, 1996.
[3] S. Kim, M. Soma, D. Risbud, “An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops,” IEEE 18th VLSI Test Symp., p231-236, 2000.
[4] S. Kim, M. Soma, “An All-Digital Built-In Self-Test for High-Speed Phase-Locked Loops,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 48 Issue: 2 , Feb. 2001 Page(s): 141 -150.
[5] B. R. Veillette, G. W. Robert, “On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 33, No. 3, pp. 483-491, March 1998.
[6] B. R. Veillette, G. W. Robert, “Stimulus generation for built-in self-test of charge-pump phase-locked loops,” in IEEE Proc. Int. Test Conf., vol. p. 698-707, 1998.
[7] S. Sunter, A. Roy, “BIST for Phase-Locked Loops in Digital Applications,” IEEE International Test Conf., p532-540, 1999.
[8] J. J. Chen, A. Roy, “PLL with On-Chip Jitter Measurement,” MS Thesis, Dpt. of
Electrical Engineering National Cheng Kung University, June 2001
[9] E. H. Armstrong, “A method of reducing disturbances in radio signaling by a system of frequency modulation,” in Proc. IRE, May 1936, vol. 24, No. 5, pp. 689-740.
[10] P. Goteti, G. Devarayanadurg, M. Soma, “DFT for Embedded Charge-Pump PLL Systems Incorporating IEEE 1149.1,” IEEE Custom Integrated Circuits Conf., Santa Clara, p210-213, May 1997.
[11] Neil H.E. West , Kamran Eshraghian “Principles of COMS VLSI Design,” Addison-Wesley Publishing Company 1993.
[12] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” Proceedings of the 1999 IEEE International Symposium on, vol.2, pp.545-548 1999.
[13] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” NY John Wiley & Sons 1994.
[14] K, Lim, C. H. Park, D. S. Kim, B. Kim, ”A low-Noise Phase-Locked Loop Bandwidth Optimization,” IEEE J. Solid-State Circuits, vol. 35, N0. 6, June 2000, pp. 807-815.
[15] C. H. Park, B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-um CMOS,” IEEE J. Solid-State Circuits, vol. 34, NO. 5, pp. 586-591 May 1999.
[16] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. Solid-State Circuits, vol. 32, pp. 289-291, Feb 1997.
[17] J. Craninckx, M. S. J. Steyaert, “A 1.8GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler,” IEEE J. Solid-State Circuits, vol. 30, NO. 12, pp. 1474-1482, December 1995.
[18] S. J. Lee and H. J. YOO, “Race Logic Architecture (RALA): A Novel Logic Concept Using the Race Scheme of Input Variables,” IEEE J. Solid-State Circuits, vol. 37, NO. 2, pp.191-201, Feb 2002.
[19] B. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y. F. Chan, T. H. Lee, M. A. Horowitz, “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE J. Solid-State Circuits, vol. 34, NO. 5, pp. 632-644, May 1999.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top