|
[1] A. Hajimiri, T. H. Lee, “The Design of Low Noise Oscillators,” Kluwer Academic Publishers, 1999. [2] B. Razavi, “Monolithic phase-locked loops and clock recovery circuits,” IEEE Press, New York, USA, 1996. [3] S. Kim, M. Soma, D. Risbud, “An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops,” IEEE 18th VLSI Test Symp., p231-236, 2000. [4] S. Kim, M. Soma, “An All-Digital Built-In Self-Test for High-Speed Phase-Locked Loops,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 48 Issue: 2 , Feb. 2001 Page(s): 141 -150. [5] B. R. Veillette, G. W. Robert, “On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 33, No. 3, pp. 483-491, March 1998. [6] B. R. Veillette, G. W. Robert, “Stimulus generation for built-in self-test of charge-pump phase-locked loops,” in IEEE Proc. Int. Test Conf., vol. p. 698-707, 1998. [7] S. Sunter, A. Roy, “BIST for Phase-Locked Loops in Digital Applications,” IEEE International Test Conf., p532-540, 1999. [8] J. J. Chen, A. Roy, “PLL with On-Chip Jitter Measurement,” MS Thesis, Dpt. of Electrical Engineering National Cheng Kung University, June 2001 [9] E. H. Armstrong, “A method of reducing disturbances in radio signaling by a system of frequency modulation,” in Proc. IRE, May 1936, vol. 24, No. 5, pp. 689-740. [10] P. Goteti, G. Devarayanadurg, M. Soma, “DFT for Embedded Charge-Pump PLL Systems Incorporating IEEE 1149.1,” IEEE Custom Integrated Circuits Conf., Santa Clara, p210-213, May 1997. [11] Neil H.E. West , Kamran Eshraghian “Principles of COMS VLSI Design,” Addison-Wesley Publishing Company 1993. [12] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” Proceedings of the 1999 IEEE International Symposium on, vol.2, pp.545-548 1999. [13] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” NY John Wiley & Sons 1994. [14] K, Lim, C. H. Park, D. S. Kim, B. Kim, ”A low-Noise Phase-Locked Loop Bandwidth Optimization,” IEEE J. Solid-State Circuits, vol. 35, N0. 6, June 2000, pp. 807-815. [15] C. H. Park, B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-um CMOS,” IEEE J. Solid-State Circuits, vol. 34, NO. 5, pp. 586-591 May 1999. [16] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. Solid-State Circuits, vol. 32, pp. 289-291, Feb 1997. [17] J. Craninckx, M. S. J. Steyaert, “A 1.8GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler,” IEEE J. Solid-State Circuits, vol. 30, NO. 12, pp. 1474-1482, December 1995. [18] S. J. Lee and H. J. YOO, “Race Logic Architecture (RALA): A Novel Logic Concept Using the Race Scheme of Input Variables,” IEEE J. Solid-State Circuits, vol. 37, NO. 2, pp.191-201, Feb 2002. [19] B. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y. F. Chan, T. H. Lee, M. A. Horowitz, “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE J. Solid-State Circuits, vol. 34, NO. 5, pp. 632-644, May 1999.
|