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研究生:朱立平
研究生(外文):Li-Ping Chu
論文名稱:語音合成器之晶片設計
論文名稱(外文):VLSI Design of Speech Synthesizer
指導教授:王駿發
指導教授(外文):Jhing-Fa Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:65
中文關鍵詞:語音合成
外文關鍵詞:PSOLASpeech Synthesis
相關次數:
  • 被引用被引用:2
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目前語音合成之應用範圍非常廣泛,例如TTS系統,發聲玩具,電子書等。可攜式裝置的語音合成需求在於合成單元佔用記憶體之多寡。
本論文即針對此點特別研究出以sub-syllable為基本合成單元使用TD-PSOLA(Time Domain Pitch Synchronous Overlap-and-Add)為合成演算法之硬體架構。在取樣頻率為8k Hz,每ㄧ點8bits時,合成單元佔用之記憶體為277k Bytes。以軟體模擬本論文之合成演算法,經測試仍具有高度之可理解度。另外對於PSOLA演算法中需求之大量三角函數值計算,本論文亦針對此點研發出快速CORDIC (Sine & Cosine mode) 演算法,此演算法求算三角函數之速度為傳統CORDIC之5倍。
未來的工作包括多重聲調的淬取,以及DAC的加入。
There are various applications of the speech synthesis system, such as TTS system, toys, electronic books, etc. For the portable speech synthesis devices, how to reduce the memory requirement is an important issue.
This paper presents a hardware architecture based on the TD-PSOLA (Time Domain Pitch Synchronous Overlap-and-Add) algorithm and the sub-syllable synthesis units. The required memory size is 277k Bytes if the sampling frequency is 8k Hz and each sample uses 8 bits. In our listening experiments, the synthesized speech is still highly understandable. As there are lots of different cosine values in the PSOLA algorithm, we adopt CORDIC algorithm to avoid the huge memory requirement. In this paper, we propose a fast CORDIC (sine & cosine mode) algorithm which is 5 times faster than the traditional CORDIC (sine & cosine mode) algorithm.
In the future work, we will focus on the multi-tone extraction and the combination of DAC.
中文摘要 iv
英文摘要 v
誌謝 vi
目錄 vii
圖目錄 ix
表目錄 xi
第一章 簡介 1
第二章 Sub Syllable-based語音合成演算法 2
2-1 演算法流程 2
2-2 語音合成單元建立 3
2-2-1 語音波形觀察 3
2-2-2 Sub-syllable粹取 6
2-2-3 能量平滑化處理 9
2-3 漢寧視窗函數(window function generator) 10
2-4 PSOLA演算法 10
2-5 Pitch scaling function 15
第三章 語音合成硬體架構設計 18
3-1 硬體整體架構 18
3-2 PSOLA架構設計 19
3-3 CORDIC division mode pitch scaling function架構設計 24
3-4 Window function generator架構設計 29
3-4-1 CORDIC Sine & Cosine mode 30
3-4-2 Proposed CORDIC Sine & Cosine algorithm & architecture 39
3-4-3 CORDIC Cosine mode應用於語音合成器時所做之調整 54
第四章 硬體比較與模擬 55
4-1 與現有語音合成硬體產品之比較 55
4-2 CORDIC Sine & Cosine mode 之比較 56
4-3 CORDIC Sine & Cosine硬體驗證 57
4-4 PSOLA硬體驗證 57
第五章 結論與未來展望 60
5-1 結論 60
5-2 未來展望 61
參考文獻 62
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