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研究生:林育弘
研究生(外文):Yu-Hong Lin
論文名稱:使用隨機多重資料加權平均法之十六位元高速數位類比轉換器
論文名稱(外文):A 16-bit, High-Speed DAC with Random Multiple Data-Weighted Averaging Algorithm
指導教授:郭泰豪
指導教授(外文):Tai-Haur Kuo
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:73
中文關鍵詞:數位類比轉換器隨機多重資料加權平均
外文關鍵詞:DACRMDWArotated walk
相關次數:
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  電流驅動式數位類比轉換器擁有高速的特性,而且現在也廣泛應用在寬頻的通訊系統。但是電流驅動式數位類比轉換器因有元件不匹配特性限制它的解析度。元件不匹配會在頻譜上造成非線性諧波而降低拒斥動態範圍值(SFDR)。這篇輪文提出一個新的演算法稱為隨機多重資料權重平均演算法可以有效克服諧波失真。隨機多重資料權重平均演算法打散諧波,將能量平均分配到noise floor而增加SFDR。我們也在這篇論文中用低複雜數位電路來實現隨機多重資料權重平均演算法。另外論文也推導出相關的數學式子和定量分析。
  我們也在這篇論文中製作一個十六位元高速數位類比轉換器。這個數位類比轉換器分成三個部分:六個最大位元(MSB)轉換成熱碼,而且這部分也使用隨機多重資料權重平均演算法;接下來五個位元(ULSB)也是轉換成熱碼,五個最小位元(LLSB)則維持使用二元碼。另外在類比部分也提出一個新的開關配置順序稱為Q的N次方旋轉式開關順序來補償元件不匹配特性。Q的N次方旋轉式開關順序能補償一階和二階的元件不匹配分布。另外也設計一個新的高速鎖栓器來增加數位類比轉換器的速度。
  這個數位類比轉換器採用台積電1P5M,0.25um製程來實現,整個晶片面積是1.9x0.9mm2。佈局後的模擬結果證實此數位類比轉換器可以操作在40MHz轉換頻率,類比電壓2.7伏特,數位電壓2.2伏特。當訊號頻率是780KHz時,SFDR可以達到102dBc。訊號頻率升到8MHz和18MHz時,SFDR分別是92dBc和84dBc。
  Current-steering DACs have intrinsic high-speed characteristics and are commonly used in wide-band communication systems today. However, element mismatch will cause harmonic distortion and thus limits their performance. This thesis proposes a new algorithm called Random Multiple Data Weighted Averaging (RMDWA) to reduce harmonic distortions due to element mismatch. RMDWA can be used to randomize tones such that spurious-free dynamic range (SFDR) and multi-tone power tone (MPTR) are increased. In addition, low-complexity digital circuit used to implement RMDWA algorithm is presented in this thesis. Performance equations and quantitative performance analyses of RMDWA are also derived.
  A 16-bit high-speed current-steering DAC is implemented in this thesis. The DAC includes a 6-bit thermometer-decoded MSB with RMDWA algorithm, a 5-bit thermometer-decoded upper LSB (ULSB) and a 5-bit binary-decoded lower LSB (LLSB). The new QN rotated-walk switching scheme is also proposed to obtain high accuracy without trimming or tuning. QN rotated-walk switching scheme can effectively compensate 1st–order and 2nd–order errors caused by current sources mismatch. In addition, a new latch is designed to increase conversion speed and reduce noise. The post-layout simulation shows that it can achieve 102/94/84dBc SFDRs under a 40-MHz clock rate with 780KHz/5MHz/18MHz signal frequencies, respectively. With 2.7V analog and 2.2V digital supplies, it has power consumption of 112mW for a clock rate of 40 MHz. The DAC is fabricated with TSMC 0.25um single-poly, five-metal process. The active die area is 1.9mm x 0.9mm.
1 Introduction 1
1.1 Motivation………………………………………………. 1
1.2 Organization…………………………………………….. 2

2 Nyquist-Rate Digital-to-Analog Converter (DAC) 4
2.1 Binary-Weighted DAC Architecture……………………. 5
2.1.1 R-2R Ladder DAC…………………………… 6
2.1.2 Charge Redistribution DAC…………….......... 7
2.1.3
Current-Steering DAC………………….......... 8
2.2 Thermometer-Coded DAC Architecture…………........... 10
2.3 Hybrid DAC Architecture………………………………. 11
2.4 What’s Important in a Wide-band DAC…………........... 12
2.4.1 Static Specification…………………………… 13
2.4.2 Spectral Specification………………………… 14
2.4.3 Conclusion……………………………………. 18

3 Random Multiple Data-Weighted Averaging Algorithm 19
3.1 Mismatch and SFDR of conventional DAC……………. 19
3.1.1 Mismatch Causes……………………………... 20
3.1.2 Current Sources Mismatch vs. SFDR………… 24
3.2 Random Multiple Data-Weighted Averaging…………… 28
3.2.1 RMDWA Algorithm…………………………... 28
3.2.2 RMDWA Performance Analysis……………… 34
3.2.3 Performance Analysis………………………… 36
3.2.4 IC Fabrication Yield Estimation…………........ 44
3.2.5 Pointer Register………………………………. 45
3.3 Implementation of RMDWA Algorithm…………............ 47
3.3.1 Segmented Architecture…………………......... 47
3.3.2 RMDWA Control Circuits…………………….. 48

4 DAC Implementation Algorithm 50
4.1 Static Performance………………………………………. 51
4.1.1 Proper Area and Bias Voltage……………........ 51
4.1.2 Distribution Current Sources…………………. 51
4.1.3 Rotated QN Walk Switching Scheme………….. 56
4.1.4 Current Cell with Triple Cascode Circuit……… 61
4.2 Dynamic Performance…………………………………... 61
4.2.1 High Speed and High Accuracy Latch………… 62
4.2.2 Tree Structure Clock…………………………… 64
4.3 Layout Implementation………………………………….. 64

5 Simulation and Measurement 67
5.1 Simulation Results………………………………………. 67
5.2 Measurement Consideration…………………………….. 67

6 Conclusion and Future Work 71
Preferences 72
1.J.Sevenhans and Z.Chang, “A/D and D/A conversion for telecommunication,” IEEE Circuits and Dev. Mag., vol. 14, pp. 32-42, Jan. 1998

2.P. Hendriks, “Specifying communications DACs,” IEEE spectrum, vol. 34, pp. 58-69, July 1997.

3.D. Mercer, “A 16bit D/A converter with increased spurious-free dynamic range,” IEEE, J. Solid-State Circuits, vol. 29, pp. 1180-1185, Oct. 1994.

4.B. Tesch and J. Garcia, “A low-glitch 14-bit 100MHz D/A converter,” IEEE, J. Solid-State Circuits, vol. 32, pp. 1465-1469, Sept. 1997.

5.Alex R. Bugeja, Bang-sup Song, “ A self-trimming 14-b 100MS/s CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.

6.R. Hester et al., “CODEC for echo-canceling full-rate ADSL modems,” in ISSCC Dig. Tech. Papers, 1999, pp. 242-243.

7.D. Groeneveld et al., “A self-calibration technique for monolithic high-resolution D/A converters,” IEEE, J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.

8.J. Bastos et. al., “A 12 bit intrinsic accuracy high-speed CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.

9.G. Van der Plas et. al., “A 14-bit intrinsic accuracy Q2 random-walk CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.

10.Y. Nakamura, T. Miki et. al., “An 80-MHz 8-bit CMOS D/A Converter,” IEEE, J. Solid-State Circuits, vol. 21, pp. 983-988, Dec. 1986.

11.R. T. Baird, T. S. Fiez, “Linearity enhancement of multibit A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. , vol. 42, pp. 753-762, Dec. 1995.

12.R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode DAC based upon rotated data weighted averaging,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1074-1084, Dec. 2000.

13.S. Chan, J. Cao er. al., “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multinit delta-sigma modulation at 8 oversampling ratio,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1820-1828, Dec. 2000.

14.K. D. Chen, H. R. Yeng, T. H. Kuo,” A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE, J. Solid-State Circuits, vol. 37, pp. 11-17, Jan. 2002.

15.R. M. Gray and T. G. Stockham, Jr., “Dithered quantizers,” IEEE Inform. Theory, vol. 39, pp. 805-812, May 1993.

16.Chi-huang and Klaas Bult, “A 10-b, 500-Msamples CMOS DAC in 0.6mm2”, IEEE, J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.

17.M. Copeland et. al., “Characterization and modeling of mismatch in MOS transistors for precision analog design”, IEEE, J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, Dec. 1986.

18.M. J. M. Pelgrom et. al. ”Matching properties of MOS transistors”, IEEE, J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.

19.Design Documents for TSMC 0.25um 1P5M Mixed Signal Process.

20.B. Razavi, “principles of Data Conversion system Design. Piscataway,” NJ: IEEE Press, 1995, pp. 62-63

21.O.Nys and R. Henderson, “An analysis of dynamic element matching techniques in sigma-delta modulation,” in Proc. ISCAS’96, Atlanta, GA, May 12-15, 1996, pp. 231-234
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1. 朱雲漢,2001,〈國民黨與台灣的民主轉型〉,《二十一世紀》,第65期,頁4-14。
2. 何俊輝、謝慧娟,2000,〈從亞太營運中心到全球運籌管理中心〉,《主計月報》,第534期,頁43-50。
3. 吳玉山,1995,〈兩岸關係對台灣經濟成長模式的影響〉,《問題與研究》,第34卷,第2期,頁1-19。
4. 宋筱元,1991,〈依賴理論的淺析〉,《警政學報》,第19期,頁504。
5. 宋學文,1998,〈議題聯結與兩岸關係之研究〉,《問題與研究》,第37卷,第2期,頁21-35。
6. 李酉潭,1997,〈邁向鞏固的民主:台灣案例〉,《中山人文社會科學期刊》,第5卷,第2期,頁161-196。
7. 阮銘,2000,〈新政府的兩岸政策─觀察與展望〉,《遠景季刊》,第1卷,第3期,頁179-199。
8. 周添城,1997,〈兩岸經貿發展的戰略思考〉,《理論與政策》,第11卷,第4期,頁86-97。
9. 周陽山,1988,〈民主化、自由化與威權轉型----國際經驗的比較〉,《中山學術論叢》,第8卷,頁79-93。
10. 明居正,1998,〈向心競爭與中華民國政黨政治之發展〉,《理論與政策》,第12卷,第2期,頁142-156。
11. 林水波、王崇斌,1996,〈公共政策論述的倫理〉,《中國行政評論》,第6卷,第1期,頁1-26。
12. 柳金財,2000,〈民進黨的台獨論述與大陸政策:過程、轉型與發展〉,《東亞季刊》,第31卷,第2期,頁101-130。
13. 柳金財,2001,〈民進黨台獨論述轉型與大陸政策調整--兼論總統選舉中政策辯論與兩岸關係發展〉,《共黨問題研究》,第26卷,第6期,頁77-91。
14. 柳金財,2001,〈論九0年代以來中華民國政府關於「一個中國論述」內涵的持續與變遷〉,《共黨問題研究》,第27卷,第4期,頁9-28。
15. 徐火炎,1993,〈選舉競爭與政治分歧結構的變遷:國民黨與民進黨勢力的消長〉,《人文及社會科學集刊》,第6卷,第1期,頁37-74。