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研究生:陳依蓉
研究生(外文):Yi-Jung Chen
論文名稱:高效能IDEA晶片之設計與研究
論文名稱(外文):The Research and Desigh of a High Performance IDEA Chip
指導教授:杜迪榕韓永祥
指導教授(外文):Dyi-Rong DuhYunghsiang S. Han
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:68
中文關鍵詞:IDEA密碼學(2^n+1)模乘法器
外文關鍵詞:IDEAcryptographymodulo (2^n+1) multiplier
相關次數:
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隨著網際網路的迅速發展,人們在此種開放環境下傳送資料的機會越來越多,因此資料的安全性也越來越重要,為避免傳送的資料被傳輸雙方之外的人所窺視或竄改,通常我們會以密碼學中的一些演算法將資料加密保護,只讓持有金鑰(key)的資料使用者,可復原經演算法加密的資料。IDEA為現今最常用,且公認為最安全的加解密演算法之一,因此,為提高其加解密速度以符合網際網路對即時傳輸的要求,在這篇論文中,我們提出一個高效能之IDEA晶片的架構。為了提高IDEA的加解密速度,我們將IDEA的一個回合以管線化的方式實現。而且我們發現,IDEA中模乘法的運算單元,為整個IDEA晶片的瓶頸所在,因此,以之前模乘器的相關論文為基礎,我們提出了一個有較高效能並適用於IDEA的模乘法器架構。在IDEA的使用情形中,我們的模乘法器與Zimmermann在1999年所提出的模乘法器相比,速度上提高了9.8%,但硬體資源的使用上不但沒有增加,反而降低了5.7%,與其它之前所提出的架構相比,我們的架構同樣有較快的速度,且不必增加硬體資源。為了要驗證我們的模乘法器之正確性,我們在Altera所研發的CPLD上做模擬,而模擬的結果正確,若在CPLD上模擬IDEA,並配合使用我們的模乘法器架構,當時脈頻率為8.25 MHz時,其加解密速度可達66 Mb/sec。

Since the rapid development of internet, the chances for
transmitting information in an opening environment are becoming
more and more. For protecting information from being retrieved by unexpected people, cryptography is widely used such that encrypted data become unrecoverable without a piece of information named a key. IDEA is one of the most popular and considered the most secure cryptography algorithm in date since the characteristic of IDEA is suitable for hardware implementation. To accommodate the speed of internat, in this thesis, we design a high performance IDEA chip. To raise its performance, we pipelined IDEA function
into four pipelined stages. Then, we found the operation of
modulo multiplication is the bottleneck of the whole chip's
performance. Base on the former works on speeding up modulo
multiplication, we designed a faster modulo multiplier which is
suitable to the implementation of IDEA. For an IDEA
implementation, the proposed design is 9.8% faster than that
by Zimmermann in 1999 while the area reduction of new design also
reaches about 5.7%, and we also compare our time delay and
area cost with some other methods. In order to verify our design
we also simulated the proposed architecture in a CPLD system
developed by Altera. The simulation results indicate that the new
design has 66 Mb/sec encryption/decryption rate under 8.25MHz
system clock rate.

Abstract i
1 Introduction 1
1.1 Background and Motivation.............1
1.2 The Former Works of Implementing IDEA.4
1.3 About This Thesis.....................5
2 International Data Encryption Algorithm (IDEA)......7
2.1 IDEA Overview...................................7
2.2 Encryption, Decryption Schemes and Subkey Generation...9
2.3 Security Analysis....................................13
3 Implementation of IDEA on VLSI...........................15
3.1 IDEA Chip Architecture Overview......................15
3.2 The Design of a Single Round.........................17
3.3 The Former Solution of Modulo Multiplicaion..........20
3.3.1 Look-Up Table Method...........................20
3.3.2 (n+1)*(n+1)-bit Multiplier Method..............21
3.3.3 Modulo (2^n+1) Adders Method...................25
4 Improvement on Designing IDEA on VLSI....................36
4.1 New Design of Modulo (2^n+1) Multiplier..............36
4.2 The Comparison.......................................51
4.3 The Implementation of an IDEA Chip.................60
4.3.1 Design Tool and Method..........................60
4.3.2 Performance and Resource Used...................61
5 Conclusion................................................63

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