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研究生:黃仕丞
研究生(外文):Shin Chen Huang
論文名稱:高頻砷化鎵元件應用之覆晶構裝發展
論文名稱(外文):The Development of Flip-Chip Package Technology for High Frequency GaAs Device Applications
指導教授:張翼張翼引用關係
指導教授(外文):Edward Y. Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:材料科學與工程系
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:覆晶構裝
外文關鍵詞:packageflip-chip
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本實驗之研究目的在發展應用於高頻砷化鎵元件之低成本覆晶構裝製程;此製程期能取代三五族傳統繁複之人工打線技術,而在高頻操作時亦能有良好的特性表現,以符合未來微波通訊高頻元件之需求。
實驗中嘗試在砷化鎵低雜訊電晶體上進行銅的金屬化及電鍍共晶銲錫接合凸塊之製程,並結合以無電電鍍鎳/銅之金屬導線及凸塊的氧化鋁基板,發展一可靠性高再現性佳之覆晶構裝製程。
論文中並對砷化鎵低雜訊電晶體之覆晶構裝製程對元件電性影響加以討論。覆晶構裝前後之高頻特性量測結果顯示本實驗應用低介電材料Benzocyclobutene (BCB)作為構裝的絕緣層能有效地抑制閘極-汲極間的回饋電容;此外,在18 GHz 的操作頻率下,構裝後之雜訊指數上升了0.54 dB,而增益則是略降了1.2 dB;本研究中並由S參數導出低雜訊電晶體小訊號等效電路,此模型之建立有助於改善元件構裝後的高頻特性表現。
總結之,本實驗完成了應用於高頻砷化鎵元件之覆晶構裝製程,並於各段製程及封裝後對電性的影響加以比較;期此應用能對下一世代高頻無線通訊在應用上有所裨益。

This thesis presents a low cost solder bumping flip chip packaging technology for high frequency GaAs device applications to replace the wire bonding technology to achieve better RF performance for the devices at high frequencies.
The developed process combines the copper-metallized UBM and electroplated eutectic solder bump on a GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor) with an electroless plated Ni/Cu post on AlN substrate. The GaAs PHEMT die is flip-chip mounted. The flip- chip assembly process is well documented which is a stable and reproducible packaging process.
DC and RF characteristics of the GaAs PHEMT before and after packaging process were investigated. The RF measurement before and after flip chip assembly reveals that low k material Benzocyclobutene (BCB) serving as the wafer passivation dielectric efficiently constrains the gate-drain feedback capacitance. In addition, at the operation frequency of 18 GHz, the gain of the flip chip packaged PHEMT drops about 1.2 dB lower and the noise figure is about 0.54 dB higher than before packaging. A small signal equivalent circuit model was made by fitting the measured s-parameters. The establishment of the device model will be helpful for improving the RF performance of the packaged device.
In conclusion, the fabrication process for flip chip packaging of high frequency GaAs device is developed. The influences of the packaging process on the electrical performance of the device were discussed as well. The results of this study would serve as the foundation for future study of the flip chip packaging technology for high frequency devices.

Chapter 1 Introduction----------------------------------------01
1.1 Motivation------------------------------------------------01
1.2 Chip scale interconnects----------------------------------02
1.2.1 Wire bonding------------------------------------------02
1.2.2 Tap automated bonding---------------------------------04
1.2.3 Flip chip bonding-------------------------------------05
1.3 Bumping methods on GaAs-----------------------------------08
1.4 The GaAs-based PHEMT for flip chip package----------------11
1.4.1 The structure of GaAs PHEMT---------------------------11
1.4.2 The fabrication process of GaAs PHEMT-----------------12
Chapter 2 Experiments and Measurements------------------------14
2.1 Wafer bumping fabrication---------------------------------14
2.1.1 Wafer cleaning----------------------------------------14
2.1.2 Formation of gold airbridge and bonding pads----------14
2.1.3 Wafer passivation-------------------------------------15
2.1.4 Solder bumping----------------------------------------17
2.1.4.1 Under bump metallurgy--------------------------17
2.1.4.2 Solder bumping---------------------------------18
2.2 Substrate metallization-----------------------------------19
2.3 Flip chip assembly----------------------------------------20
2.3.1 Wafer sawing------------------------------------------21
2.3.2 Flip chip placement-----------------------------------21
2.3.2.1 Die feeding and pick-up------------------------21
2.3.2.2 Alignment and die placement--------------------22
2.3.2.3 Solder reflow----------------------------------22
2.4 Measurements----------------------------------------------23
2.4.1 DC measurement----------------------------------------23
2.4.1.1 Current-voltage curve--------------------------23
2.4.1.2 Transconductance (gm)--------------------------24
2.4.2 RF measurements----------------------------------24
2.4.2.1 S-parameters-----------------------------------24
2.4.2.2 Equivalent circuit model-----------------------25
2.4.2.3 Noise figure-----------------------------------26
Chapter 3 Results and Discussions-----------------------------28
3.1 Thin metal etching----------------------------------------28
3.2 Solder reflow---------------------------------------------29
3.3 DC characteristics----------------------------------------30
3.3.1 I-V characteristics-----------------------------------30
3.3.2 Transconductance gm-----------------------------------31
3.4 RF characteristics----------------------------------------31
3.4.1 S-parameters measurement------------------------------32
3.4.2 Equivalent circuit model------------------------------32
3.4.3 Noise figure------------------------------------------33
Chapter 4 Conclusions-----------------------------------------35
References----------------------------------------------------37
Tables
Figures

[1] S. Masuda, T. Hirose, S. Yokokawa, M. Nishi, S. Iijima, K. Ono, and Y. Watanabe, IEEE GAAS Digest (2001) 118-121.
[2] Y. —F. Wu, P.M. Chavarkar, ,. Moore, P. Parikh, and U.K. Mishra, IEDM 01 (2001) 378-380.
[3] O.Vendier, S. George, J-P. Fraysse, E. Rogeaux, C. Drevon, J-L, Cazaux, D, Floriot, N. Caillas-Devignes, H. Blanck, W, Doser, P. Auxemery, W. de Ceuninck, R. Petersen, N. Haese, P-A, Rolland, IEEE GaAs Digest (2000) 157-159.
[4] Y.-F. Wu, D. Kapolnek, J. Ibbetson, P.Parikh, B. P. Keller, and U.K. Mishra, IEEE MTT-S Digest (2000) 963-965.
[5] T. Tanaka, H. Furukawa, H. Nagata, D. Ueda, Solid-State Electronics 43 (1999) 1405-1411.
[6] K. Maruhashi, M. Ito, H. Kusamitsu, Y. Morishita and K. Ohata, IEEE MTT-S Digest (1998) 1095-1098.
[7] P. Cameron, W. Pan, C. Hanz, R. Nicklaus, IEEE MTT-S Digest (1997) 889-892.
[8] J.E. Sergent and C.A. Harper, “Hybrid Microelectronics Handbook”, McGraw-Hill, New York, 1995.
[9] P.E Garrou and I. Turlik, “Multichip Module Technology Handbook”, McGraw-Hill,1998
[10] R.R. Tummala, E. J. Rymaszewski, and A. G. Klopfenstein, “Microelectronics Packaging Handbook,” London, U.K.:Chapman &
Hall, 1996
[11] D.A. Doane and P.D. Franzon, “Multichip Module Technologies and Alternatives: The Basics”, Van Nostrand Reinhold, 1993.
[12] D. S. Patterson, P. Elenius and J. A. Leal, Advances in Electronic Packaging, Vol. 1 (1997) 337-351.
[13] C. L. Lessen, Electronic Components andTechnology Conference (1996) 1056-1058.
[14] Adaptation from a 1994 IBM Microelectronics Presentation.
[15] G.A. Rinne, Electronic Components and Technology Conference, (1997) 240-247
[16] K J. Puttlitz, K. A. Stalter and P. A. Totta, IEEE Transactions on
Components, Packaging, and Manufacturing Technology, CPMT-C
(1998) 182-188
[17] A.J.G Strandjord, R.H. Heisand, and J.N. Bremmer, IEEE Trans. Comp., Packag., Manufact. Technol. (1994) 374-386
[18] J.H. Lau, “Flip Chip Technologies”, McGraw-Hill, New York, 1996
[19] T. Akashi et al., IEEE/CPMT International electronics manufacturing technology symposium (1997) 319-325
[20] T. Foley, Advanced Packaging, Vol. 8, No. 2, (1992) 1999
[21] R. Boulanger, J. Carbin and D. Viza, Advance Packaging, (1997)
39-42
[22] Koch, J. A. Nelson, ”Metallographic Etching”, American Society for Metal, 1978
[23] T. Tanaka, H. Furukawa, H. Nagata, D. Ueda, Solid-State Electronics 43 (1999) 1405-1411

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