最近幾年來，非同步處理器成為新一代計算機架構的熱門研究方向。非同步處理器在執行時並不是藉由全域的時脈來達到同步，而是藉由通訊協定來替代全域的時脈。基本上，非同步處理器與同步處理器相較起來，有可能帶來一些好處，當然也會有新的挑戰。因此，我們對非同步處理器有相當大的興趣，並且想設計一個非同步處理器。
　　我們嘗試以MIPS R2000指令集架構為基礎，設計一個非同步處理器。在與另一位同學的共同研究中，我們設計出一個稱作為AMIPS的非同步處理器，並且以SystemC實作。SystemC是一個類似於Verilog的硬體描述語言，而且它融入了C++語言的物件導向之特性。
　　本論文主要是負責AMIPS非同步處理器中之指令擷取單元與解碼單元之設計，其他部分則由另一位同學所完成。在本論文中，我們會介紹非同步架構的相關觀念與研究、我們的設計、以及如何以SystemC完成實作。我們各自完成自己的部分，並將它們整合起來。最後，我們以每個指令實測AMIPS，以及利用數個自行編寫的程式做較完整的測試，所有測試的結果皆符合所預期的功能。

Asynchronous processors have become a new aspect of modern computer architecture research in these years. An asynchronous processor is by no means synchronized by global clock. However, it employs communication protocols doing synchronization instead. Basically, in contrast with synchronous processors, asynchronous processors possess certain advantages while definitely encounter new challenges. Therefore, we were interested in asynchronous processor, and we desired to design it thus.
We design an asynchronous processor based on the MIPS R2000 instruction set architecture. Specifically, in the co-study with another research-mate, we accomplish the design of an asynchronous processor named Asynchronous MIPS (AMIPS). Actually, the AMIPS is implemented by SystemC. The SystemC is a hardware description language like Verilog, which contains C++ object-oriented features in it.
In this thesis we achieve part of AMIPS including instruction fetch unit and decoding unit, with other parts fulfilled by the research-mate. We introduce the concept and research of asynchronous architecture, our design of AMIPS, and how to implement it by using SystemC in the thesis. The two parts of design and implementation of the asynchronous processor are carried out separately, and then they are integrated. Finally, we check the AMIPS by each and almost every instruction, and also test it by several programs coded by us. All of the results of these checks and tests are matched the expected functionality.

Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Introduction to Asynchronous Processors 1
1-3 Introduction to SystemC 4
1-4 Organization of This Thesis 6
Chapter 2 Related Work 7
2-1 Micropipelines 7
2-2 Micronets 9
2-3 Communication Protocols 12
2-4 Data Encoding 17
2-5 The Classes of Asynchronous Circuits 19
2-6 Arduous Problems of Asynchronous Processors Designs 19
2-6-1 Branching 20
2-6-2 Exception or Interrupt Handling 20
2-6-3 Data Forwarding 21
2-6-4 Communication with Off-Chip Memory 21
Chapter 3 Design of the Proposed AMIPS 23
3-1 Overview of the AMIPS 23
3-2 Design of the IF Stage 25
3-3 Design of the ID Stage 26
3-4 Design of the PC controller 30
3-5 Design of the Register File 32
Chapter 4 Implement AMIPS by Using SystemC 36
4-1 Concepts of SystemC 36
4-1-1 Modules and Hierarchy 36
4-1-2 Processes 41
4-1-3 Ports and Signals 42
4-1-4 Data Types 43
4-1-5 Using the Synthesizable Subset 44
4-2 Implement the IF Stage by Using SystemC 46
4-3 Implement the ID Stage by Using SystemC 47
4-4 Implement the PC Controller by Using SystemC 48
4-5 Implement the Register File by Using SystemC 50
Chapter 5 Verification of the AMIPS 52
5-1 Verification at Stage Level 52
5-1-1 Verification of the IF Stage 52
5-1-2 Verification of the ID Stage 54
5-1-3 Verification of the PC Controller 55
5-1-4 Verification of the Register File 57
5-2 Verification at Instruction Level 57
5-3 Verification at Program Level 58
Chapter 6 Conclusion and Future Work 62
References 63

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