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研究生:吳門書
研究生(外文):Men-Shu Wu
論文名稱:非同步處理器之指令擷取單元與解碼單元之設計
論文名稱(外文):The Design of Instruction Fetching and Decoding of Asynchronous Processor
指導教授:陳昌居
指導教授(外文):Chang-Jiu Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:64
中文關鍵詞:非同步處理器
外文關鍵詞:Asynchronous ProcessorAMIPS
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  最近幾年來,非同步處理器成為新一代計算機架構的熱門研究方向。非同步處理器在執行時並不是藉由全域的時脈來達到同步,而是藉由通訊協定來替代全域的時脈。基本上,非同步處理器與同步處理器相較起來,有可能帶來一些好處,當然也會有新的挑戰。因此,我們對非同步處理器有相當大的興趣,並且想設計一個非同步處理器。
  我們嘗試以MIPS R2000指令集架構為基礎,設計一個非同步處理器。在與另一位同學的共同研究中,我們設計出一個稱作為AMIPS的非同步處理器,並且以SystemC實作。SystemC是一個類似於Verilog的硬體描述語言,而且它融入了C++語言的物件導向之特性。
  本論文主要是負責AMIPS非同步處理器中之指令擷取單元與解碼單元之設計,其他部分則由另一位同學所完成。在本論文中,我們會介紹非同步架構的相關觀念與研究、我們的設計、以及如何以SystemC完成實作。我們各自完成自己的部分,並將它們整合起來。最後,我們以每個指令實測AMIPS,以及利用數個自行編寫的程式做較完整的測試,所有測試的結果皆符合所預期的功能。

Asynchronous processors have become a new aspect of modern computer architecture research in these years. An asynchronous processor is by no means synchronized by global clock. However, it employs communication protocols doing synchronization instead. Basically, in contrast with synchronous processors, asynchronous processors possess certain advantages while definitely encounter new challenges. Therefore, we were interested in asynchronous processor, and we desired to design it thus.
We design an asynchronous processor based on the MIPS R2000 instruction set architecture. Specifically, in the co-study with another research-mate, we accomplish the design of an asynchronous processor named Asynchronous MIPS (AMIPS). Actually, the AMIPS is implemented by SystemC. The SystemC is a hardware description language like Verilog, which contains C++ object-oriented features in it.
In this thesis we achieve part of AMIPS including instruction fetch unit and decoding unit, with other parts fulfilled by the research-mate. We introduce the concept and research of asynchronous architecture, our design of AMIPS, and how to implement it by using SystemC in the thesis. The two parts of design and implementation of the asynchronous processor are carried out separately, and then they are integrated. Finally, we check the AMIPS by each and almost every instruction, and also test it by several programs coded by us. All of the results of these checks and tests are matched the expected functionality.

Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Introduction to Asynchronous Processors 1
1-3 Introduction to SystemC 4
1-4 Organization of This Thesis 6
Chapter 2 Related Work 7
2-1 Micropipelines 7
2-2 Micronets 9
2-3 Communication Protocols 12
2-4 Data Encoding 17
2-5 The Classes of Asynchronous Circuits 19
2-6 Arduous Problems of Asynchronous Processors Designs 19
2-6-1 Branching 20
2-6-2 Exception or Interrupt Handling 20
2-6-3 Data Forwarding 21
2-6-4 Communication with Off-Chip Memory 21
Chapter 3 Design of the Proposed AMIPS 23
3-1 Overview of the AMIPS 23
3-2 Design of the IF Stage 25
3-3 Design of the ID Stage 26
3-4 Design of the PC controller 30
3-5 Design of the Register File 32
Chapter 4 Implement AMIPS by Using SystemC 36
4-1 Concepts of SystemC 36
4-1-1 Modules and Hierarchy 36
4-1-2 Processes 41
4-1-3 Ports and Signals 42
4-1-4 Data Types 43
4-1-5 Using the Synthesizable Subset 44
4-2 Implement the IF Stage by Using SystemC 46
4-3 Implement the ID Stage by Using SystemC 47
4-4 Implement the PC Controller by Using SystemC 48
4-5 Implement the Register File by Using SystemC 50
Chapter 5 Verification of the AMIPS 52
5-1 Verification at Stage Level 52
5-1-1 Verification of the IF Stage 52
5-1-2 Verification of the ID Stage 54
5-1-3 Verification of the PC Controller 55
5-1-4 Verification of the Register File 57
5-2 Verification at Instruction Level 57
5-3 Verification at Program Level 58
Chapter 6 Conclusion and Future Work 62
References 63

[1] Tse-Hao Lee. The Design and Implementation of Asynchronous Processor Simulator. MS Thesis, Computer Science and Information Engineering, National Chiao Tung University, 2001
[2] G. Kane and J. Heinrich. MIPS RISC Architecture. Prentice Hall, 1992.
[3] D. A. Patterson and J. L. Hennessy. Computer Organization & Design: The Hardware/Software Interface 2nd. Morgan Kaufmann, 1998
[4] D. A. Patterson and J. L. Hennessy. Computer Architecture: A Quantitative Approach 2nd. Morgan Kaufmann, 1996.
[5] C. J. Myers. Asynchronous Circuit Design. Wiley-Interscience, 2001.
[6] All Contributors of OSCI. SystemC Version 2.0 User's Guide. OSCI, 2001. See http://www.systemc.org.
[7] Synopsys Company. Describing Synthesizable RTL in SystemC. Synopsys Company, 2001. See http://www.synopsys.com.
[8] S.Y. Liao. Towards a new standard for system-level design. In Proceedings of the Eighth International Workshop on Hardware/Software Codesign, pages 2-6, 2000.
[9] G. Arnout. SystemC standard. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pages 573-577, 2000.
[10] I.E. Sutherland. Micropipelines. Communications of the ACM, 32(6): 720-738, June 1989.
[11] D.K. Arvind, R.D. Mullins and V.E.F. Rebello. Micronets: a model for decentralizing control in asynchronous processor architectures. In Proceedings of Second Working Conference on Asynchronous Design Methodologies, pages 190-199, 1995.
[12] S.B. Furber, P. Day, J.D. Garside, N.C. Paver and J.V. Woods. AMULET1: a micropipelined ARM. In Digest of Papers on Compcon Spring '94, pages 476-485, 1994.
[13] J.V. Woods, P. Day, S.B. Furber, J.D. Garside, N.C. Paver and S.Temple. AMULET1: an asynchronous ARM microprocessor. IEEE Transactions on Computers, 46(4): 385-398, Apr. 1997.
[14] W.B. Puah, B.S. Suparjo, R. Wagiran and R. Sidek. Rapid prototyping asynchronous processor. In IEEE International Conference on Semiconductor Electronics, pages 223-227, Nov. 2000.
[15] S. Hauck. Asynchronous design methodologies: an overview. Proceedings of the IEEE, 83(1): 69-93, Jan. 1995.
[16] A. Davis and Steven M. Nowick. An Introduction to Asynchronous Circuit Design. Technical Report UUCS-97-013, Department of Computer Science, University of Utah, Sep. 1997.

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