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研究生:許志強
研究生(外文):Chih-Chiang Shiu
論文名稱:非同步處理器之執行單元記憶體存取單元與寫回單元之設計
論文名稱(外文):The Design of Execution, Memory Access, and Writeback of Asynchronous Processor
指導教授:陳昌居
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:66
中文關鍵詞:非同步處理器
外文關鍵詞:Asynchronous Processor
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  • 點閱點閱:141
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最近幾年來,非同步處理器成為新一代計算機架構的熱門研究方向。非同步處理器在執行時並不是藉由全域的時脈來達到同步,而是藉由通訊協定來替代全域的時脈。基本上,非同步處理器與同步處理器相較起來,有可能帶來一些好處,當然也會有新的挑戰。因此,我們對非同步處理器有相當大的興趣,並且想設計一個非同步處理器。
我們嘗試以MIPS R2000指令集架構為基礎,設計一個非同步處理器。在與另一位同學的共同研究中,我們設計出一個稱作為AMIPS的非同步處理器,並且以SystemC實作。SystemC是一個類似於Verilog的硬體描述語言,而且它融入了C++語言的物件導向之特性。
本論文主要是負責AMIPS非同步處理器中之執行單元、記憶體存取單元、與寫回單元之設計,其他部分則由另一位同學所完成。在本論文中,我們會介紹非同步架構的相關觀念與研究、我們的設計、以及如何以SystemC完成實作。我們各自完成自己的部分,並將它們整合起來。最後,我們以每個指令實測AMIPS,以及利用數個自行編寫的程式做較完整的測試,所有測試的結果皆符合所預期的功能。

Asynchronous processors have become a new aspect of modern computer architecture research in these years. An asynchronous processor is by no means synchronized by global clock. However, it employs communication protocols doing synchronization instead. Basically, in contrast with synchronous processors, asynchronous processors possess certain advantages while definitely encounter new challenges. Therefore, we were interested in asynchronous processor, and we desired to design it thus.
We design an asynchronous processor based on the MIPS R2000 instruction set architecture. Specifically, in the co-study with another research-mate, we accomplish the design of an asynchronous processor named Asynchronous MIPS (AMIPS). Actually, the AMIPS is implemented by SystemC. The SystemC is a hardware description language like Verilog, which contains C++ object-oriented features in it.
In this thesis we achieve part of AMIPS including execution unit, memory access unit, and write back unit, with other parts fulfilled by the research-mate. We introduce the concept and research of asynchronous architecture, our design of AMIPS, and how to implement it by using SystemC in the thesis. The two parts of design and implementation of the asynchronous processor are carried out separately, and then they are integrated. Finally, we check the AMIPS by each and almost every instruction, and also test it by several programs coded by us. All of the results of these checks and tests are matched the expected functionality.

CHAPTER 1 INTRODUCTION 1
1-1 MOTIVATIONS 1
1-2 INTRODUCTION TO ASYNCHRONOUS PROCESSORS 1
1-3 INTRODUCTION TO SYSTEMC 4
1-4 ORGANIZATION OF THIS THESIS 7
CHAPTER 2 RELATED WORK 9
2-1 MICROPIPELINES 9
2-2 MICRONETS 10
2-3 FOUR-PHASE DATA BUNDLED COMMUNICATION 13
2-4 REPRESENTATION OF DATA 14
2-5 ARDUOUS PROBLEMS OF ASYNCHRONOUS PROCESSORS DESIGNS 16
2-5-1 Branching 17
2-5-2 Exception or Interrupt Handling 17
2-5-3 Data Forwarding 18
2-5-4 Communication with Off-chip Memory 19
2-6 CONCLUDING REMARKS 20
CHAPTER 3 DESIGN OF THE PROPOSED AMIPS 21
3-1 OVERVIEW OF AMIPS ARCHITECTURE 21
3-2 FETCH, DECODING STAGES AND PC CONTROLLER 23
3-3 EXECUTION STAGE 23
3-3-1 Protocol of Execution stage 25
3-3-2 Exe Unit 28
3-3-3 Delay-Insensitive Carry-Lookahead Adder 29
3-4 MEMORY ACCESS AND WRITEBACK STAGE 32
3-4-1 Protocol of MEM&WB stage 32
3-4-2 MEM&WB Unit 33
3-5 MEMORY FILE 35
3-5-1 Protocol of Memory File 35
CHAPTER 4 IMPLEMENTATION USING SYSTEMC 38
4-1 MODULES AND HIERARCHY 38
4-2 PROCESSES 40
4-2-1 Method Process 41
4-2-2 Thread Process 41
4-2-3 Clocked Thread Process 42
4-3 DESIGN TESTBENCHES IN SYSTEMC 43
4-4 PORTS, SIGNALS AND DATA TYPES 44
4-5 SIMULATION AND DEBUGGING USING SYSTEMC 46
4-5-1 Simulation Control 46
4-5-2 Debugging in SystemC 47
4-6 CONVERTING TO A SYNTHESIZABLE SUBSET 48
4-7 CONTENTS OF MEMORY FILE 51
4-8 CONCLUDING REMARKS 52
CHAPTER 5 VERIFICATION RESULTS 53
5-1 LOCAL VERIFICATION 53
5-1-1 Design TestBenches For Execution stage 53
5-1-2 Design testbenches for MEM & WB stage 55
5-2 GLOBAL VERIFICATION ENVIRONMENT 56
5-3 VERIFY THE INSTRUCTION SET 57
5-4 VERIFY THE AMIPS BY PROGRAM 58
5-4-1 Produce the Instruction File 58
5-4-2 Verification 59
CHAPTER 6 CONCLUSION AND FUTURE WORK 64
REFERENCES 65

[1] SYSTEMC Version 2.0 Beta-2 User’s Guide, 1996.
[2] T. Werner, V. Akella, “Asynchronous processor survey,” IEEE Computer Vol 30, Issue 11, pp. 67-76, Nov. 1997.
[3] Sutherland I.E., “Micropipelines,” Communications of the ACM, Vol.32, No.6, pp. 720-738, June 1989.
[4] D. K. Arvind et al., “Micronets: A Model for Decentralising Control in Asynchronous Processor Architectures,” Asynchronous Design Methodologies, Proceedings, Second Working Conference, pp. 190-199, 1995.
[5] S.B. Furber; P. Day, J.D. Garside; N.C. Paver; J.V. Woods, “AMULET1: a micropipelined ARM,” Compcon Spring '94, Digest of Papers, pp. 476-485, 1994.
[6] J.V. Woods; P. Day, S.B. Furber, J.D. Garside, N.C. Paver, S. Temple, “AMULET1: an asynchronous ARM microprocessor,” Computers, IEEE Transactions on Computers, Vol. 46 Issue 4, pp. 385-398, Apr. 1997.
[7] S.B. Furber; J.D. Garside; P. Riocreux; S. Temple; P. Day, Jianwei Liu; N.C. Paver, “AMULET2e: an asynchronous embedded controller,” Proceedings of the IEEE, Vol. 87, Issue 2, pp. 243-256, Feb. 1999.
[8] D.W. Lloyd, J.K. Garside, “A Practical Comparison of Asynchronous Design Styles,” Seventh International Symposium on, Asynchronous Circuits and Systems, pp. 36-45, 2001.
[9] Lloyd, D.W.; Garside, J.D.; Gilbert, D.A. “Memory faults in asynchronous microprocessors,” Fifth International Symposium on, Asynchronous Circuits and Systems, pp. 71-80, 1999
[10] Describing Synthesizable RTL in SystemC, Version 1.0, May 2001.
[11] Fu-Chiung Cheng, Stephen H. Unger, “Self-Timed Carry-Lookahead Adders,” IEEE Transactions on Computers, pp. 659-672, July 2000.
[12] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990.
[13] Gerry Kane, Joe Heinrich, MIPS RISC Architecture, 1992.

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