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研究生:江尚旻
研究生(外文):Jiang Shang Min
論文名稱:DesignandVerificationofPCIBusSystemintegratedintoIAM2000S
論文名稱(外文):整合於以IAM2000S微處理器為主之系統的PCI滙流排架構的設計及驗證
指導教授:吳 全 臨單 智 君林 瀛 寛
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:61
中文關鍵詞:微處理器
外文關鍵詞:PCI
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隨著製程及晶片設計技術的進步,設計一個內含百萬千萬電晶體的晶片已成了可行之事.而其中以系統晶片最為熱門也是未來的趨視,所以本計畫以設計一顆以ARM為中央處理器兼具發展其週邊之系統為目的,其中包括快取記憶體,記憶體系統,記憶體管理單元,及橫跨不同滙流排協定的橋接元件.
本論文重點即著重在設計一個介於系統滙流排及週邊滙流排之間的橋接元件,此橋接元件意在用於就不同滙流排協定之間的訊號轉換,由於所使用的週邊滙流排和原本撘配系統滙流排的並不一樣,所以必須去克服兩者之間的差異點.除此之外,本論文亦加入了簡易的驗證系統,去檢測運行於此兩者滙流排系統協定的資料流工作. 
With advancement of process and technology of chip design , it is possible to design a chip which contains millions transistors.It is obviously that the system-on-a-chip is the future trend of this field ,therefore our project is to design a system which ARM-9 like processor including cache , memory system MMU and the bridge crossing the different bus system domain.
And the major contribution of this thesis is to implement a bridge across two different bus system , one is AHB system bus and another is PCI peripheral bus.The main job of the bridge is to convert the different signal information of different bus system during each transaction.However it is hard to replace the original peripheral bus APB with the current used one PCI.Besides , the verification system to the transaction across different bus domain is also implemented.By this thesis , we can know that the performance of such architecture adapted to the SOC architecture during operation.
中文摘要 I
英文摘要 II
誌謝 III
表目錄 IV
圖目錄 V
Chapter 1. Introduction 1
Chapter 2. System Architecture 2
2.1 System Block 2
2.1.1 Microprocessor 2
2.1.2 AHB_Master_Interface 3
2.1.3 Cache 3
2.1.4 PU and WB 4
2.1.5 AHB/PCI Bridge 4
2.2 Choosing the right bus 5
2.2.1 System Bus 5
2.2.2 Peripheral Bus 6
2.3 Transaction 6
Chapter 3. AMBA system 8
3.1 Overview of the AMBA Specification 8
3.1.1 AHB 9
3.1.2 ASB 9
3.1.3 APB 9
3.2 How AHB works 9
3.2.1 Bus Interconnection 10
3.2.2 Transfer Type 11
3.2.3 Burst Operation 13
3.2.4 Transfer Size 13
3.2.5 Slave Trnasfer Response 13
3.3 AHB Master Interface 16
3.4 AHB Slave Interface 17
3.5 Arbiter Interface 18
Chapter 4. PCI Architecture 19
4.1 PCI Feature 19
4.2 PCI Operation 20
4.2.1 Address Phase 21
4.2.2 Data Phase 21
4.3 PCI Interface 22
4.4 PCI Signal 23
4.5 PCI Arbitration 26
4.5.1 Arbitration Algorithm 27
4.5.1.1 Hidden Bus Arbitration 27
4.5.1.2 Bus Parking 27
4.5.1.3 Bus State 28
4.6 Transaction Type 29
4.6.1 Interrupt Acknowledge 29
4.6.2 Special Cycle 30
4.7 PCI Protocol 30
4.7.1 Read Transfer 31
4.7.2 Write Transfer 32
Chapter 5. Design of AHB/PCI Bridge 33
5.1 Introduction 33
5.2 Interface 33
5.2.1 AHB Slave 34
5.2.2 PCI Master 34
5.3 Finite State Machie 35
5.3.1 One Clock Latency 36
5.4 Protocol Converting 37
5.4.1 Signal Converting 37
5.4.2 Transaction Termination 38
5.4.2.1 Initiator Termination 38
5.4.2.2 Target Termination 39
5.4.3 Response 40
5.5 Memory Mapping 41
5.5.1 Memory Transaction 41
5.5.2 IO Transaction 42
5.5.3 Configuration Addressing 42
5.5.4 Memory Allocation 43
5.6 Burst Mode 45
Chapter 6. Implementation of Psuedo PCI Slave 47
6.1 Interface 47
6.2 Finite State Machie 48
6.2.1 State Transition 48
6.3 Parity Check 49
6.4 Parameters of Pseudo PCI Slave 49
Chapter 7. System Testing 52
7.1 Overview of Testing Environment 52
6.2.1 PCI Transaction Verification 52
6.2.1 System Verification 56
Chapter 8. Conclusoin 61
參考文獻 VI
[1] Steve Furber, “ARM System-on-chip Architecture”,Second Edition , Addison-Wesley , 2000
[2] “AMBA Specification Rev2.0 “, Copyright ARM Limited .
[3] David A. Patterson, John L. Hennessy, “ Computer Architecture. A Quantitative Approach”,Second Edition, Morgan Kaufmann Publishers, 1996
[4] 王仕杰,”Design and Implementation of Controller of an Embedded RISC Microprocessor with DSP Capability”, 國立交通大學資訊工程學系碩士論文,2001
[5] 鄭信源,”Verilog 硬體描述語言數位電路-設計實務”, 儒林 , 2000
[6] Charles H. Roth, Jr., “ Digital Systems Design Using VHDL” , PWS Publishing Company
[7] David A. Patterson, John L. Hennessy, “ Computer Organization & Design . The Hardware/Software Interface”, Second Edition , Morgan Kaufmann Publishers, 1998
[8] Mark Gordon Arnold , “ Verilog Digital Computer Design — Algorithm into Hardware”, Prentice Hall
[9] Douglas J Smith , “ HDL Chip Design”, Doone Publications
[10] Tom Shanley, “ Pentium Pro Processor System Architecture” , MindShare, Inc.
[11] Henry Chang , Larry Cooke , Merrill Hunt , Grant Martin Andrew McNelly and lee Todd , “ Surviving the SOC Revolution — A Guide to Platform-Based Design”, Kluwer Academic Publishers
[12] Tom Shanley and Don Anderson , “ PCI System Architecture”, Fourth Edition , MindShare, Inc.
[13] 黃明權, “ Mixed Mode Verification for 32-bit Microprocessor Core”, 國立交通大學資訊工程學系碩士論文,2001
[14] IEEE Standard 1364 Verilog Hardware Description Language, 2001
[15] Kyeong Koel Ryu , Eung Shin , and Vincent J.Monney , “A Comparison of Five
Different Multiprocessor SoC Bus Architecture“ , 1999
[16] Luc Semeria , Abhijit Ghosh , “Methodology for Hardware/Software
Co-verification in C/C++” , 1999
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