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研究生:蔡佳洲
研究生(外文):Jia-Jou Tsai
論文名稱:ARM9微處理機之省電設計
論文名稱(外文):Low Power Techniques for ARM9TDMI
指導教授:單智君
指導教授(外文):Jean, J.J. Shann
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:60
中文關鍵詞:省電設計位元活動運算單元嵌入式系統
外文關鍵詞:ARM ProcessorLow PowerSwitching ActivityFunction UnitEmbedded System
相關次數:
  • 被引用被引用:1
  • 點閱點閱:313
  • 評分評分:
  • 下載下載:75
  • 收藏至我的研究室書目清單書目收藏:4
可攜式設備的快速成長,為嵌入式系統帶來了許多新的應用與挑戰。省電設計在整個系統規劃上為相當重要的課題。根據研究發現,在執行某段程式過程中,運算單元會執行一段時間後閒置,也就是說運算單元不需一直保持於忙碌狀態,這種狀況提供了省電設計的可能。因此,若能將不需使用的運算單元關閉,則可節省不必要之能量消耗。
在本論文中,我們探討如何降低各運算單元的活動,來減少系統的耗能。我們提出了三個方法,分別為:當指令執行時適當的關閉不需使用的運算單元、對於Dummy運算的特殊處理、和減少False-condition指令所造成運算單元不必要的活動。
架構上的設計重點包含指令解碼器的加強、運算元選擇單元的建立以及資料路徑的修改等三部分。藉由事先分析各指令的行為,指令解碼器可決定出指令在執行時不需使用之運算單元。透過運算元選擇單元來保持上次運算的值;當運算單元不需運作時,可將上一次運算的值送入運算單元以減少運算單元狀態的轉換所產生的耗能。另外,我們對算術運算邏輯單元和移位器的資料路徑做了小幅度的修改;在發生某些特別運算時,能將運算元適當的繞徑來減少運算單元內部的耗能。
我們以ARM9TDMI為實驗對象並針對上述機制進行模擬。模擬結果顯示,相較於原本ARM9TDMI上的各運算單元的活動率,在算術邏輯單元上可節省30%,移位器可節省60%,而乘法器則高達99%以上。
The market of portable devices is growing rapidly, and many applications and challenges appear in the design of an embedded system. Low power design becomes an important issue for embedded system design. Observation reveals that function units are sometimes idle for a period of time after serving a burst of computation requests. This provides us an opportunity to design low power architecture. If we can reduce the number of signal switching activities, the unnecessary power consumption will be saved.
In this thesis, we propose three methods to reduce switching activities of function unit. The proposed methods are freezing unused function unit for instruction execution, bypassing dummy operation, and freezing all function units for false-condition instruction.
The architecture design includes enhancement of the instruction decoder, Operand-Selection unit (OSU) design, and data-path modification. By profiling instruction behaviors in advance, the instruction decoder can determine the unused function units for an instruction, and then freeze these units in the following cycle. The OSU is used to keep a previous operand of a function unit and restore it to the function unit when the unit will not work in the next cycle. In addition, we modify the data-path of ALU and shifter to reduce the power consumption by bypassing some operands when encountering special operations.
We simulate our proposed methods on ARM9TDMI and compare the switching activity for each function unit. Simulation results show that the reduction of switching activity for ALU using our mechanism is 30% of the original, and that for shifter is 60%, and that for multiplier is 99%.
摘要 i
ABSTRACT ii
誌 謝 iv
Table of Contents v
List of Figures vii
List of Tables ix
Chapter 1 Introduction 1
1.1 Research Motivation 2
1.1.1 Power Consumption Distribution 2
1.1.2 Instruction Behaviors 4
1.2 Research Goal 4
1.3 Organization of This Thesis 5
Chapter 2 Background and Related Work 6
2.1 Overview of Embedded Processors 6
2.2 ARM9 Architecture 7
2.2.1 Instruction Set Architecture 8
2.2.2 Instruction Formats 13
2.2.3 Processor Organization 15
2.3 Power Consumption in CMOS Circuits 18
2.4 Previous Researches Related to Switching Activity Reduction 19
2.4.1 Pre-computation Architecture 20
2.4.2 Dynamic-range Determination (DRD) Unit 21
Chapter 3 Proposed Low Power Techniques 25
3.1 Freezing Unused Function Unit 25
3.1.1 Instruction Behavior Analysis 26
3.1.2 Architecture Overview 27
3.1.3 Decoding Stage Modification 29
3.1.4 Execution Stage Modification 30
3.2 Bypassing Dummy Operation 34
3.2.1 Dummy Operation Analysis 35
3.2.2 Data-path Modification 36
3.3 Low Power Enhancement with Condition Code Consideration 39
3.3.1 Checking of Condition Code in Decoding Stage 40
3.3.2 Checking of Condition Code in Execution Stage 41
3.4 Summary 43
Chapter 4 Simulation Environment and Results 44
4.1 Benchmark Suite 44
4.1.1 Criteria for Selecting Benchmarks 44
4.1.2 MediaBench Benchmarks 45
4.2 Simulation Methods 48
4.2.1 Simulation Toolset 48
4.2.2 Simulation Flow 49
4.3 Simulation Results 51
4.3.1 Dynamic Instruction Ratio 51
4.3.2 Reduction of Switching Activity 52
Chapter 5 Conclusions and Future Work 58
[1] http://www.arm.com
[2] Manfred Schlett, “Trends in Embedded-Microprocessor Design,” Computer, IEEE 1998.
[3] Bill Moyer, “Low-Power Design for Embedded Processors,” Proceedings of the IEEE, on page(s):1576 - 1587, Nov. 2001.
[4] Steve Furber, “ARM System-on-chip Architecture,” Harlow, England ;New York:Addison-Wesley, 2000.
[5] Simon Segars, “Low Power Design Techniques for Microprocessors,” ISSCC, Feb 4th 2001.
[6] Advanced RISC Machines Ltd., “ARM Architecture Reference Manual”, June 2000.
[7] Advanced RISC Machines Ltd., “ARM7TDMI Data Sheet”, July 1996.
[8] Advanced RISC Machines Ltd., “ARM9TDMI Technical Reference Manual”, March 2000.
[9] Mazhar Alidina, Jose Monteiro, Srinivas Devadas and Abhijit Ghosh, “Precomputation-based Sequential Logic Optimization For Low Power,” IEEE/ACM International Conference on Computer-Aided Design, 1994.
[10] Yi-Wen Wu, Oscal T.-C. Chen and Ruey-Liang Ma, “A Low-Power Digital Signal Processor Core by Minimizing Inter-Data Switching Activity,” Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, on page(s):172 - 175 vol.1, 2001.
[11] Sandy Wang, Yi-Wen Wu, Oscal T.-C. Chen and Ruey-Liang Ma, “Low-Power Multipliers by Minimizing Inter-Data Switching Activities,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, on page(s):88 - 92 vol.1, 2000.
[12] Robin Sheen, Sandy Wang, Oscal T.-C. Chen and Ruey-Liang Ma, “Power Consumption of a 2''s Complement Adder Minimized by Effective Dynamic Data Ranges,” ISCAS ''99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, on page(s):266 - 269 vol.1, 1999.
[13] C. Lee, M. Potkonjak, and W. H. M.-Smith, “MediaBench:A Tool for Evaluating and Synthesizing Multimedia and Communications Systems”, 30th Annual ACM/IEEE International Symposium on Microarchitecture, 1997.
[14] http://www.cs.ucla.edu/~leec/mediabench/applications.html
[15] Advanced RISC Machines Ltd., “ARM Software Development Toolkit Version 2.50 User Guide”, November 1998.
[16] Advanced RISC Machines Ltd., “ARM Software Development Toolkit Version 2.50 Reference Guide”, November 1998.
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