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研究生:許鈺鼎
研究生(外文):Yu Tin Hsu
論文名稱:IAM2000S系統之AMBAAHB匯流排架構實現與驗證
論文名稱(外文):Implementation and Verification of AMBA AHB Bus Architecture on IAM2000S System
指導教授:吳 全 臨林 瀛 寬單 智 君
指導教授(外文):Chuan-Lin WuYin-Kuan LinJyh-Jiun Shann
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:67
中文關鍵詞:前瞻微處理器匯流排架構前瞻高效能匯流排前瞻高效能匯流排認證系統
外文關鍵詞:AMBAAHBAHB master verification system
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由於半導體製造技術的迅速發展,一個晶片上所能夠容納的電晶體數急遽的增加,使得系統晶片(System On Chip,簡稱SOC)成為晶片設計上的趨勢。系統晶片上能夠整合各種不同功能特性的矽智產 (IP),因此複雜度也較以往單一功能晶片相對的提升,如何以最有效率的方式來產生最大的用途是SOC的關鍵考量因素。IAM2000S系統的目的是設計一個系統晶片,其中整合了微處理器、記憶體管理單元、寫入暫存器以及晶片匯流排架構,使其能夠在短時間內以其為平台發展嵌入式系統及其應用程式。
重複使用的特性、彈性及模組化的設計、驗證所需的時間、未來的周邊設備的整合度…等特性是在選擇匯流排時考量的課題。AMBA AHB(前瞻微處理器架構之前瞻高性能匯流排)是一個被廣泛運用的晶片匯流排,與其他的晶片匯流排架構相比,其功能受到大眾的肯定及認同,市佔率相當高,並且支援模組化的設計,相當符合IAM2000S系統匯流排(System bus)的需要。
此篇論文提出一個實現AHB匯流排的方法,包含AHB master interface的實現方式、AHB arbiter的演算法及一個用來驗證AHB master interface的匯流排功能正確性的驗證系統,其中的實作經驗及驗證環境可應用至實現其他晶片匯流排上,能夠有效的縮短系統晶片發展的時程並且提高競爭力。

Due to the rapid progress in semiconductor manufacture technology, the continuing increase of the transistor numbers makes SOC (system on Chip) possible to integrate numerous functions onto a silicon chip. An SOC design combines several IP for effective cost and greater performance. IAM2000S system is an SOC platform that combines the processor, memory system and the on-chip bus architecture. In choosing the bus architecture, there are many key topics need to be considered such as the reuse possibility, flexibility and modular design, the verification effort, and the integration period with the time-to-market issue.
AMBA AHB is a widely preferred and flexible bus which meets the requirements and its performance has been proven with many complex chip architectures. It has been widely used in the industry and supports modular design, so it can provide shorter system integration period. The contribution of this thesis is to bring up the implementation methodology of AMBA AHB bus and an efficient verification environment on the AMBA AHB master interface. It can be referenced and applied on other bus architecture.

摘 要 I
Abstract II
誌 謝 III
Contents IV
Figures and Tables VI
Chapter1 AMBA 1
1.1 Overview of AMBA Specification 1
1.2 Introduction to AMBA AHB 4
1.2.1 The Difference between AHB and ASB 4
1.3 IAM2000S System Overview 6
1.3.1 AHB Interconnection 6
1.4 IAM2000S System Architecture 8
Chapter2 AHB Bus Master Interface Design 9
2.1 AHB Master 9
2.1.1 The Dummy Master 9
2.2 IAM2000S Master Interface 10
2.2.1 Pins of Interface 10
2.2.2 Cache Miss 11
2.2.3 Write Buffer 12
2.2.4 Data Coherency between Cache and Memory 12
2.3 Handshaking Protocols 14
2.3.1 Handshaking with MMU 14
2.3.2 Handshaking with Write Buffer 15
2.3.3 IAM2000S AHB Master Interface Architecture 17
2.4 Basic AHB Trasnfer 18
2.5 FSM of AHB Bus master Interface 19
Chapter3 AHB Arbiter and Decoder Design 21
3.1 AHB Arbiter and Decoder 21
3.2 IAM2000S System Arbiter 22
3.2.1 Pins of IAM2000S System Arbiter 22
3.2.2 Request Bus Access 23
3.2.3 Grant Bus Access 23
3.2.4 Burst Transfer 23
3.2.5 Lock Transfer 24
3.2.6 Arbitration Scheme 24
3.2.7 Next Master Selection 27
3.3 FSM of IAM2000S system Arbiter 28
3.4 IAM2000S System Decoder 29
3.4.1 Address Mapping of IAM2000S System 29
Chapter4 Slave Response Issue 30
4.1 Overview 31
4.2 Two-cycle Response 32
4.3 Response Handling of IAM2000S AHB Master Interface 34
4.4 Response Handling of IAM2000S AHB Arbiter 36
Chapter5 Verification on the AHB master interface 38
5.1 Verification Environment 39
5.2 Intorduction to Verilog PLI 41
5.3 Verification Methodology 42
5.3.1 PU and WB Behavioral Model 43
5.3.2 AHB Slave Behavioral Model 44
5.3.3 Automatic Test Pattern Generator 46
5.4 Verification reports 47
5.4.1 Notes of verification 48
5.4.2 Result of Verification 49
5.4.3 Coverage Analysis and Advantages 50
5.4.4 Future Extension of Verification 51
Chapter6 Synthesis Statistic 52
Chapter7 Conclusion 57
Reference 58

[1] ARM ,“ARM9E-S Technical Reference Manual” , 1999
[2] ARM ,“AMBA Specification v2.0”, 1999
[3] Charles H. Roth, Jr., “ Digital Systems Design Using VHDL” , PWS Publishing Company
[4] David A. Patterson , John L. Hennessy , “ Computer Architecture. A Quantitative
Approach” , Second Edition , Morgan Kaufmann Publishers , 1996
[5] Douglas J.Smith , “HDL Chip Design”, 1999
[6] IEEE Standard 1364 Verilog Hardware Description Language, 2001
[7] Kyeong Koel Ryu , Eung Shin , and Vincent J.Monney , “A Comparison of Five
Different Multiprocessor SoC Bus Architecture“ , 1999
[8] Luc Semeria , Abhijit Ghosh , “Methodology for Hardware/Software
Co-verification in C/C++” , 1999
[9] Henry Chang , Larry Cooke , Merrill Hunt , Grant Martin Andrew McNelly and
lee Todd , “ Surviving the SOC Revolution : A Guide to Platform-Based Design”,
Kluwer Academic Publishers
[10] Steve Furber, “ARM: System-On-Chip Architecture”, 2000
[11] 王仕杰 , ”Design and Implementation of Controller of an Embedded RISC
Microprocessor with DSP Capability” , 國立交通大學資訊工程學系碩士論
文 , 2001
[12] 黃明權 , ”Mixed Mode Verification for 32-bit Microprocessor Core” , 國立
交通大學資訊工程學系碩士論文 , 2001
[13] IAM2000S Micro-architectu re Specification

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