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研究生:蔡長委
研究生(外文):Tsai Chang-Wei
論文名稱:IAM2000S微處理器之快取記憶體與寫入緩衝器的設計與實作
論文名稱(外文):Design and Implementation of Cache and Write Buffer for IAM2000S Microprocessor
指導教授:吳全臨林瀛寬單智君
指導教授(外文):Wu Chuan-LinLin Yin-KuanShann Jyh-Jiun
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:35
中文關鍵詞:快取記憶體寫入緩衝器
外文關鍵詞:CacheWrite Buffer
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  • 下載下載:24
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近年來,由於系統晶片(System-on-Chip,簡稱SoC)的蓬勃發展,加上對矽智產元件(IP)重覆使用的觀念,基於這樣的設計發展的趨勢,本論文提出了一個在既有的微處理器核心架構前提下,整合週邊環境和外部匯流排成為一個矽智產元件的設計和實作,為目前業界普遍採用的方法。
本論文是設計出具有信號處理能力的嵌入式微處理器IAM2000S的快取記憶體架構,結合記憶體管理單元和寫入緩衝器,讓IAM2000S能夠從快取記憶體得到正確的指令和資料。在設計架構和寫入策略以及取代策略等不同設計考量下,如何設計一個具有最佳效能且相容於IAM2000S微處理器架構是本論文的目標。
除了在硬體架構的設計之外,輔助以設計自動化工具來模擬和分析快取記憶體和寫入緩衝器的正確性和效能評估,整合IAM2000S成為一個完整的微處理器。

Recently, basis the rapid development of System-on-Chip (SoC) and the concept of reusing Intellectual Property (IP), the thesis propose the design and implementation of architecture with an existent microprocessor core and integrated peripheral environment and external bus to be an IP. This is commonly used in ICs industry.
In this thesis, we propose the design of cache architecture for an embedded RISC microprocessor with DSP capability, IAM2000S. With the integration of memory management unit and write buffer, IAM2000S can access the instructions and data fast and correctly. In the different consideration of cache architecture, write policies and replacement strategies, the major objective is to design a memory access system with best performance and compatible with IAM2000S.
Besides the design of hardware architecture, we simulate and analysis the accuracy of cache and write buffer by computer-aid-design tool. We provide the integration methodology for the IAM2000S to be a complete microprocessor.

Chapter1 Introduction
1.1 Motivation
1.2 Objective
1.3 Thesis Organization
Chapter2 Background Knowledge
2.1 IAM2000S SOC System Architecture
2.2 Internal Function Block
2.3 Introduction to Cache
2.4 Introduction to Write Buffer
Chapter3 Caches Organization
3.1 Overview
3.2 Cache address
3.3 Set-associativity
3.4 Replacement Strategies
3.5 Write Policies
3.6 Implementation
3.6.1 Design of Replacement Strategy
3.6.1.1 Design of LRU Replacement
3.6.1.2 Implementation of LRU Replacement
3.6.2 Design of Instruction Cache
3.6.2.1 Instruction Cache Organization
3.6.2.2 Instruction Cache Operation
3.6.3 Design of Data Cache
3.6.3.1 Data Cache Organization
3.6.3.2 Data Cache Operation
3.7 Performance Evaluation
Chapter4 Write Buffer Organization
4.1 Objective
4.2 FSM of Write Buffer
4.3 Implementation
4.4 Simulation Result
Chapter5 Conclusion
5.1 Accomplishment
5.2 Future Work

[1] Steve Furber, “ARM: System-On-Chip Architecture”, 2000
[2] ARM ,“AMBA Specification v2.0”, 1999
[3] ARM ,“ARM9E-S Technical Reference Manual” , 1999
[4] Douglas J.Smith , “HDL Chip Design”, 1999
[5] IEEE Standard 1364 Verilog Hardware Description Language, 2001
[6] Charles H. Roth, Jr., “ Digital Systems Design Using VHDL” , PWS Publishing Company
[7] Kyeong Koel Ryu , Eung Shin , and Vincent J.Monney , “A Comparison of Five Different Multiprocessor SoC Bus Architecture“ , 1999
[8] David A. Patterson , John L. Hennessy , “ Computer Architecture: A Quantitative Approach” , Second Edition , Morgan Kaufmann Publishers , 1996
[9] Henry Chang , Larry Cooke , Merrill Hunt , Grant Martin Andrew McNelly and lee Todd , “ Surviving the SOC Revolution : A Guide to Platform-Based Design”, Kluwer Academic Publishers
[10] IAM2000S Micro-architecture Specification

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