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研究生:李介文
研究生(外文):Jam Wem Lee
論文名稱:二矽烷複晶矽薄膜及四氟化碳電漿預處理技術在製備薄氧化層之研究
論文名稱(外文):High Reliability Thin Oxides Prepared with the Disilane-based Polysilicon Films and CF4 Plasma Pre-treatment
指導教授:李崇仁李崇仁引用關係雷添福
指導教授(外文):Chung_Len LeeTan Fu Lei
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:90
語文別:英文
論文頁數:117
中文關鍵詞:二矽烷複晶矽鎳矽化物電漿預處理穿隧氧化層複晶矽氧化層
外文關鍵詞:DisilaneNi-polycideTEOSCF4 pasmaTunnel oxidepolyoxieN2O plasmaTEOS oxide
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論文摘要
隨著3C時代的來臨,個人數位助理(PDA)越來越普及。然而在PDA的系統中,擁有高密度及低操作電壓的非揮發性記憶體是必須的。為了提高記憶體的密度及降低操作電壓,必須有高可靠度的薄複晶矽氧化層及穿隧氧化層。但是,氧化層厚度的降低可能會受限於SILC效應,因此,專家預測,穿隧氧化層厚度薄化的極限會在6.0nm。所以,如果要降低此元件的工作電壓的話,必須提高穿隧氧化層的穿隧電流且在不增加SILC及可靠度的前提下。
為了達成前面幾個需求,我提出了幾個方法並證明其可行性。首先,我提出了利用二矽烷複晶矽薄膜以及其堆疊薄膜作為製作複晶矽氧化層之基材;而氧化層成長之方式包括利用氧氣或氧化二氮在高溫爐中成長,利用TEOS在低壓爐管中成長並加以快速退火步驟。我發現,利用此薄膜所製出來的薄複晶矽氧化層擁有極高的可靠度,與製作在傳統複晶矽薄膜上的氧化層相較,此氧化層有較高的崩潰電場分佈,尤其是超過十倍以上的崩潰電荷分佈。這些改善,相信是由於較低的電子捕捉所導致的,較低的電子捕捉則是由於本複晶矽具有超平坦的表面以及高濃度的氮含量所致,尤其在氮含量這項因素上,我們發現了只有在含氮閘極氧化層才會有的電洞捕捉現象。所以,我們猜測氮參雜在本氧化層的可靠度中必定佔了相當大的影響。為了將表面平坦度及氮含量的因素分開,以及找出為何本法會有較高的氮含量,我們提出了一個疊型複晶矽薄膜結構。利用此結構,我們發現了在成長複晶矽氧化層時,氮含量的多寡確實上是個決定性的因子,此外我們也發現,較高的氮含量是由於二矽烷複晶矽特殊的結構所致。
其次,我亦將此薄膜應用於製作鎳矽化物上,我發現由於此薄膜具有特殊的晶體結構,所以製作出來的鎳矽化物有較高的熱穩定度及較低的鎳穿透至氧化層。
最後,為了提高氧化層之穿隧電流,我利用一個CF4電漿預先氟化的製程步驟,來降低氧化層的電子能障高度,以提高穿隧電流,且因為氟化的影響,氧化層的SILC效應被有效的抑制了。由於利用此法,氟只分佈於矽表面,所以不會影響電晶體通道的特性。為了證明這一點,我將此氧化層應用於電晶體的製作上,結果發現電晶體通道的特性不會因而衰減,反而有較高的可靠度。
在此論文中,我提出了十分適合下一世代非揮發性記憶體的製程材料,並證明了其可行性。相信其對未來的記憶體微小化必有相當大的助益。
Abstract
For mobile electronics systems, the EEPROM of high density, low operating voltage and good reliability is needed. To meet the above requirements, a high reliable polyoxide, a Ni-polycide of good thermal stability, and a tunnel oxide with a large tunneling current but superior reliability are studied in this thesis.
Firstly, a thin polyoxide thermally grown on the disilane-based polysilicon is studied. It is found that the oxides grown on the disilane one has a better Ebd, a higher Qbd and a lower electron-trapping rate. The improvement is due to the smoother interface at polyoxide/Poly-I of the disilane one; however, will be degraded by the effect of oxidation-enhanced interface roughness. In diminishing the drawback of thermally oxidation, a TEOS oxide deposited on disilane-based polysilicon and its stacked structures followed with a rapid thermal annealing in an N2O ambient are proposed and investigated. The nitrided oxide is found to have a much better Ebd distribution than that fabricated on the conventional polysilicon film. i.e. the silane-based polysilicon film. The most exciting result is that Qbd distributions of the disilane one is above one order higher, this improvement is attributed to a much smaller electron-trapping rate caused from the smoother surface and higher nitrogen incorporation.
The nitrogen incorporation could be an important factor in improving the polyoxides. In our proposed oxides, a hole trapping phenomenon, which could only observed in heavily nitrided oxides, is found and can largely affect electron trapping and Qbd properties. In order to separate the effects of interface roughness from nitrogen incorporation, the disilane-based stacked structures are designed. It is demonstrated that the higher nitrogen bonding in the oxides, which dominates the improvement of polyoxides, is ascribed to the textured structure of the disilane polysilicon film. Additionally, a lower resistance of the disilane polysilicon could be also attributed to the grains structure.
The thermal stability of a Ni-polycide is strongly related to the polysilicon what it is formed. Thus, to obtain a Ni-polycide of good thermal stability, the Ni-polycide formed on the disilane-based polysilicon film is also investigated. It is found that owing to the textured structure, the Ni-polycide form on the disilane polysilicon film has a better thermal stability. In further suppressing Ni-penetration to improve the reliability of gate oxides, the disilane-based stacked structures are designed to meliorate thermal stability of Ni-polycide and suppress Ni-penetration at once. As a result, by using the structures, the stability of Ni-polycide can maintain up to 800℃ with barely no Ni penetrating.
Finally, a tunnel oxide, a fluorinated oxide with higher tunneling current but lower SILC effect was prepared and investigated. Those superior characteristics of the oxide are proven to cause from the high fluorine incorporating in the oxide; moreover, for the fluorine distributes only over the surface of the silicon, the degradation of channel properties can be eliminated. In proving the previous statement, MOSFETs are fabricated in this thesis to study the channel mobility; it is found that the channel mobility of the MOSFET’s is unchanged by the additional plasma process. Furthermore, a better reliability of the transistor is also found in the experiment, which can attribute to the F incorporation.
In this thesis, the thin oxides prepared on the disilane-based polysilicon films and CF4 pretreated silicon are demonstrated to have characteristics meet the requirements of scaled down and embedded nonvolatile memories. Moreover, Ni-polycide formed on the disilane-based stacked polysilicon films is found having a better thermal stability and superior suppression of Ni-penetration, which can reduce gate oxide degradation during the Ni-polycide gate fabricating.
Abstract of the thesis
In English………………………………………………………………
In Chinese……………………………………………………………..
4
6
Chapter 1. Introduction of the Thesis…………………………………………………8
1.1 Background ……………………………………………………………...8
1.2 Motivation11
1.3 Thesis organization12
Chapter 2. The Thin Oxides Grown on Disilane-based Polysilicon……………18
2.1.Introduction………………………………………………………18
2.2.Experiments………………………………………………………18
2.3.Results and Discussion…………………………………………..19
2.4.Conclusions………………………………………………………..20
Chapter 3. High Reliability Polyoxide Fabricated by Using TEOS Oxide Deposited on Disilane Polysilicon Film……………………………...
29
3.1.Introduction………………………………………………………29
3.2.Experiments………………………………………………………30
3.3.Results and Discussion…………………………………………..31
3.4.Conclusions………………………………………………………..34
Chapter 4. The Nitrogen Incorporation Enhancement in the RTN2O annealed TEOS Oxide on the Disilane-based Polysilicon Films……………...
45
4.1.Introduction………………………………………………………45
4.2.Experiments………………………………………………………45
4.3.Results and Discussion…………………………………………..46
4.4.Conclusions………………………………………………………..49
Chapter 5. Improvements in Both Thermal Stability of Ni-Silicide and Electrical Reliability of Gate Oxides by Using Stacked Polysilicon Gate Structure
60
5.1.Introduction………………………………………………………60
5.2.Experiments………………………………………………………61
5.3.Results and Discussion…………………………………………..62
5.4.Conclusions………………………………………………………..64
Chapter 6. Thin Tunnel Oxide Grown on Silicon Substrate Pre-treated by CF4 Plasma………………………………………………………………………74
6.1.Introduction………………………………………………………74
6.2.Experiments………………………………………………………75
6.3.Results and Discussion…………………………………………..75
6.4.Conclusions………………………………………………………..78
Chapter 7. Highly Reliable Low Temperature Ultra Thin Oxides Grown by using N2O Plasma ………………………………………………………………..95
7.1.Introduction………………………………………………………95
7.2.Experiments………………………………………………………96
7.3.Results and Discussion…………………………………………..97
7.4.Conclusions………………………………………………………..99
Chapter 8. Conclusions and further recommendations of the thesis……………….108
8.1 Conclusions108
8.2 Further recommendations:
8.2.1 Ultra thin polyoxides on Disilane-based polysilicon films…….109
8.2.2 Plasma grown oxides in low temperature devices……………..109
Reference:110
Chapter 1…………………………………………………………………….111
Chapter 2……………………………………………………………………112
Chapter 3…………………………………………………………………….113
Chapter 4……………………………………………………………………..114
Chapter 5…………………………………………………………………….115
Chapter 6……………………………………………………………………..116
Chapter 7…………………………………………………………………….117
Chapter 1:
[1.1]. Roberto Versari, Augusto Pieracci, Damiana Morigi, and Bruno Ricco., “ Fast Tunneling Programming Memories” , IEEE Trans. On Electron Device, vol. 47, NO. 6, JUNE 2000.
[1.2]. R. Kramer, " Consumer electronics as silicon engine," in IEDM tech. Dig., 1999, pp. 3-7.
[1.3].Runnion, E.F.; Gladstone, S.M., IV; Scott, R.S.; Dumin, D.J.; Lie, L.; Mitros, “Limitations on oxide thicknesses in flash EEPROM applications”, J. Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International , 1996
Page(s): 93 -99
[1.4]. Lai, S., “Tunnel oxide and ETOX/sup TM/ flash scaling limitation “, Nonvolatile Memory Technology Conference, 1998 Proceedings. Seventh Biennial IEEE , 1998 Page(s): 6 —7
[1.5]. C. S. Lai, T. F. Lei, and C. L. Lee, “The Characteristics of polysilicon oxide grown in pure N2O” IEEE Transactions on Electron Devices, vol. 43, p.326-331,1996.
[1.6]. C. H. Kao, C. S. Lai, and C. L. Lee “ The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid thermal Annealing” IEEE Electron Devices lett, vol. 44, NO. 11. Nov. 1997.
[1.7]. C. H. Kao, C. S. Lai and C. L. Lee, “ The TEOS CVD Oxide Deposited on Phosphorus in-situ/POCl3 Doped Polysilicon with Rapid Thermal Annealing in N2O, “ IEEE Trans. Electron Device, vol. 45, no.9, p.1927, Sep. 1998.
[1.8].Ushiyama, M.; Satoh A.; Kume H., “Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory”, Symposium on VLSI Technology, 1999. Digest of Technical Papers. , 1999 Page(s): 23 —24
[1.9] Shye Lin Wu; De Ming Chiao; Chung Len Lee; Tan Fu Lei., “Characterization of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on silicon”, IEEE Trans. on Electron Devices, Volume: 43, Feb. 1996 Page(s): 287 —294
[1.10] Kow-Ming Chang; Chii-Horng Li; Bao-Sheng Sheih; Ji-Yi Yang; Shih-Wei Wang; Ta-Hsun Yeh. ,“A new simple and reliable method to form a textured Si surface for the fabrication of a tunnel oxide film “, IEEE Electron Device Letters , Volume: 19 , May 1998 Page(s): 145 —147
[1.11] R. Mukai, S. Ozawa and H. Yagi, “ Compatibility of NiSi in the self-aligned silicide process for deep submicrometer device,“ Thin Soild Films, vol. 270, p.567, 1995.
[1.12] R. K. Shukla and J. S. Multani, Proc. 4th VLSI Multilevel Interconnection conf., p.470, 1987.
[1.13] S. Pramanick, B. K. Patnaik and G. A. Rozgonyi, Mater. Res. Soc. Symp. Proc., vol. 309, p.475, 1993.
[1.14] Kow-Ming Chang; Chii-Horng Li; Bao-Sheng Sheih; Ji-Yi Yang; Shih-Wei Wang; Ta-Hsun Yeh. ,“A new simple and reliable method to form a textured Si surface for the fabrication of a tunnel oxide film “, IEEE Electron Device Letters , Volume: 19 , May 1998 Page(s): 145 —147
[1.15]Buller, J.F.; Bandyopadhyay, B.; Garg, S.; Patel, N. “Improved EEPROM tunnel- and gate-oxide quality by integration of a low-temperature pre-tunnel-oxide RCA SC-1 clean”, IEEE Trans. on Semiconductor Manufacturing, Volume: 9 Issue: 3 , Aug. 1996 Page(s): 471 —476
[1.16]. Lo, G.Q.; Ting, W.; Ahn, J.H.; Kwong, D.-L.; Kuehne, J.”Thin fluorinated gate dielectrics grown by rapid thermal processing in O2 with diluted NF3”, IEEE Transactions on Electron Devices, Volume: 39, Jan. 1992 Page(s): 148 —153
[1.17].Ghidini, G.; Drera, D.; Maugain, F., “F contamination effects on intrinsic and extrinsic gate oxide reliability“, Integrated Reliability Workshop, 1995. Final Report., International , 1995 Page(s): 92 —97
chapter 2.
[2.1]. C. S. Lai, T. F. Lei, and C. L. Lee, “The Characteristics of polysilicon oxide grown in pure N2O” IEEE Transactions on Electron Devices, vol. 43, p.326-331,1996.
[2.2]. L. Faraone, “ Thermal SiO2 films on N+ polycrystalline silicon : Electrical conduction and breakdown, “ IEEE Trans. Electron Devices, vol. 33, p.1785, Nov. 1986.
[2.3]. S. L. Wu. T. Y. Lin, C. L. Lee, and T. F. Lei, “Electrical characteristics of textured polysilicon oxide prepared by a low-temperature wafer loading and N2 preannealing process,” IEEE Electron Decice Let., vol.14, p.113, 1994
[2.4]. S. L. Wu, C. Y. Chen, T. Y. Lin , C. L. Lee, T. F. Lei and M. S. Liang,” Investigation of the polarity asymmetry on the electrical characteristics of thin polyoxides grown on n+ polysilicon , “ IEEE Trans. Electron Devices, vol. 44, p.153, Jan. 1997.
[2.5]. C. H. Kao, C. S. Lai, and C. L. Lee “ The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid thermal Annealing” IEEE Electron Devices lett, vol. 44, NO. 11. Nov. 1997.
[2.6]. C. H. Kao, C. S. Lai and C. L. Lee, “ The TEOS CVD Oxide Deposited on Phosphorus in-situ/POCl3 Doped Polysilicon with Rapid Thermal Annealing in N2O, “ IEEE Trans. Electron Device, vol. 45, no.9, p.1927, Sep. 1998.
[2.7]. L. Faraone, R. Vibronek, and J. Mc Ginn,” Characterization of therimally oxidized n+ polycrystalline silicon,” IEEE Trans. Electron Devices, Vol. ED-32, p.577, Mar. 1985.
[2.8]. C. H. Hong, C. Y. Park. And H. J. Kim, “Structure and crystallization of low pressure chemical vapor deposition silicon films using Si2H6 gas,” J. Appl. Phys., vol. 71, pp.5427, 1992[10]
[2.9]. S. Hasegawa ,S. Sakamoto, T. Inokuma, and Y. Kurata “structure of recrystal silicon films prepared from amorphous silicon deposited using disilane.” Appl. Phys.Lett. 62(11),15 March 1993.
[2.10]. E. G. Lee,J. J. Kim “Investigation of microstructure and grain grownth of polycrystalline silicon deposited using silane and disilane.” Thin Solid Films . 226(1993)123-128.
[2.11]. H. Hwang, W. Ting, D. L. Kwong, and J. Lee, “ Electrical and reliability characteristics of ultrathin oxynitride dielectric prepared by rapid thermal processing in N2O” in IEDM Tech. Dig. 1990, p421-424.
Chapter3:
[3.1]. C. S. Lai, T. F. Lei, and C. L. Lee, “The Characteristics of polysilicon oxide grown in pure N2O” IEEE Transactions on Electron Devices, vol. 43, p.326-331,1996.
[3.2]. L. Faraone, “ Thermal SiO2 films on N+ polycrystalline silicon : Electrical conduction and breakdown, “ IEEE Trans. Electron Devices, vol. 33, p.1785, Nov. 1986.
[3.3]. S. L. Wu. T. Y. Lin, C. L. Lee, and T. F. Lei, “Electrical characteristics of textured polysilicon oxide prepared by a low-temperature wafer loading and N2 preannealing process,” IEEE Electron Decice Let., vol.14, p.113, 1994
[3.4]. S. L. Wu, C. Y. Chen, T. Y. Lin , C. L. Lee, T. F. Lei and M. S. Liang,” Investigation of the polarity asymmetry on the electrical characteristics of thin polyoxides grown on n+ polysilicon , “ IEEE Trans. Electron Devices, vol. 44, p.153, Jan. 1997.
[3.5]. C. H. Kao, C. S. Lai, and C. L. Lee “ The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid thermal Annealing” IEEE Electron Devices lett, vol. 44, NO. 11. Nov. 1997.
[3.6]. C. H. Kao, C. S. Lai and C. L. Lee, “ The TEOS CVD Oxide Deposited on Phosphorus in-situ/POCl3 Doped Polysilicon with Rapid Thermal Annealing in N2O, “ IEEE Trans. Electron Device, vol. 45, no.9, p.1927, Sep. 1998.
[3.7]. L. Faraone, R. Vibronek, and J. Mc Ginn,” Characterization of therimally oxidized n+ polycrystalline silicon,” IEEE Trans. Electron Devices, Vol. ED-32, p.577, Mar. 1985.
[3.8]. C. H. Hong, C. Y. Park. And H. J. Kim, “Structure and crystallization of low pressure chemical vapor deposition silicon films using Si2H6 gas,” J. Appl. Phys., vol. 71, pp.5427, 1992[10]
[3.9]. S. Hasegawa ,S. Sakamoto, T. Inokuma, and Y. Kurata “structure of recrystal silicon films prepared from amorphous silicon deposited using disilane.” Appl. Phys.Lett. 62(11),15 March 1993.
[3.10]. E. G. Lee,J. J. Kim “Investigation of microstructure and grain grownth of polycrystalline silicon deposited using silane and disilane.” Thin Solid Films . 226(1993)123-128.
[3.11]. H. Hwang, W. Ting, D. L. Kwong, and J. Lee, “ Electrical and reliability characteristics of ultrathin oxynitride dielectric prepared by rapid thermal processing in N2O” in IEDM Tech. Dig. 1990, p421-424.
[3.12]. M. Bhat, J. Kim, J. Yan, G. W. Yoon, L. K. Han, and D. L. Kwong, “ MOS characteristics of ultrathin NO-grown oxynitride” IEEE Electron Device Lett. vol 15 NO. 10 Oct. 1994, p421
[3.13].S. Hasegawa, S. Watanabe, T. inokuma, and Y. Kurata, “ Structure and grain boundary defects of recrystallized silicon films prepared from amorphous silicon deposited using disilane” J. Appl. Phys. 77 (5), 1 march 1995.
Chapter 4:
[4.1]. C. H. Kao, C. S. Lai, and C. L. Lee “ The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid thermal Annealing” IEEE Electron Devices lett, vol. 44, NO. 11. Nov. 1997.
[4.2]. L. Faraone, “ Thermal SiO2 films on N+ polycrystalline silicon : Electrical conduction and breakdown,” IEEE Trans. Electron Devices, vol. ED-33, p.1785, Nov. 1986.
[4.3]. S. L. Wu , T. Y. Lin, C. L. Lee, and T. F. Lei, “ Electrical characteristics of textured polysilicon oxide prepared by a low-temperature wafer loading and N2 preannealing process,” IEEE Electron Device Let, vol.14, p.113, 1994
[4.4]. S. L. Wu, C. Y. Chen, T. Y. Lin, C. L. Lee, T. F. Lei and M. S. Liang,” Investigation of the polarity asymmtry on the electrical characteristics of thin polyoxides grown on n+ polysilicon,” IEEE Trans. Electron Devices, Vol. 44, p153, Jan. 1997.
[4.5]. C. H. Kao, C. S. Lai, and C. L. Lee “ The TEOS CVD Oxide Deposited on Phosphorus In Situ Doped Polysilicon with Rapid thermal Annealing” IEEE Electron Devices lett, vol. 44, NO. 11. Nov. 1997.
[4.6]. C. H. Kao, C. S. Lai and C. L. Lee, “ The TEOS CVD Oxide Deposited on Phosphorus in-situ/POCl3 Doped Polysilicon with Rapid Thermal Annealing in N2O, “ IEEE Trans. Electron Device, vol. 45, no.9, p.1927, Sep. 1998.
[4.7]. J. W. Lee, C. L. Lee, T. F. Lei and C. S. Lai, “ Highly Reliable Polyoxide Fabricated by Using TEOS Oxide Deposited on Disilane Polysilicon Films” will be published on IEEE Trans Electron Device April 2001.
[4.8]. E. G. Lee, J. J. Kim “Investigation of microstructure and grain grownth of polycrystalline silicon deposited using silane and disilane.” Thin Solid Films . 226(1993)123-128.
[4.9]. H. Hwang, W. Ting, D. L. Kwong, and J. Lee, “ Electrical and reliability characteristics of ultrathin oxynitride dielectric prepared by rapid thermal processing in N2O” in IEDM Tech. Dig. 1990, p421-424.
[4.10]. M. Bhat, J. Kim, J. Yan, G. W. Yoon, L. K. Han, and D. L. Kwong, “ MOS characteristics of ultrathin NO-grown oxynitride” IEEE Electron Device Lett. vol 15 NO. 10 Oct. 1994, p421
Chapter 5:
[5.1] J. B. Lasky, J. S. Nakos, O. J. Cain and P. J. Geiss, “Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2,” IEEE Trans. Electron Devices, vol.38, p. 262,1991.
[5.2] C. Y. Ting, F. M. d’Heurle, S. S. Iyer, and P.M. Fryer, “High temperature process limitation on TiSi2, ” J. Electrochem. Soc., vol. 133, no. 12, p. 2621, 1986.
[5.3] J. F. Chen and L. J. Chen, “Morphological stability of TiSi2 on polycrystalline silicon,“ Thin Solid Films, vol.293, p. 34,1997.
[5.4] S. A. Jang, T. K. Kim, I. S. Yeo, H. S. Kim, and S. K. Lee, “Effects of thermal process after silicidation on the performance of TiSi2/polysilicon gate device,” IEEE Trans. Electron Devices, vol. 46, no. 12, p.2353, Dec. 1999.
[5.5] R. Mukai, S. Ozawa and H. Yagi, “ Compatibility of NiSi in the self-aligned silicide process for deep submicrometer device,“ Thin Soild Films, vol. 270, p.567, 1995.
[5.6] R. K. Shukla and J. S. Multani, Proc. 4th VLSI Multilevel Interconnection conf., p.470, 1987.
[5.7] S. Pramanick, B. K. Patnaik and G. A. Rozgonyi, Mater. Res. Soc. Symp. Proc., vol. 309, p.475, 1993.
[5.8] S. L. Wu, C. L. Lee, T. F. Lei, “ Suppression of boron penetration induced Si/ SiO2 interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET, “ IEEE Trans. Electron Device Lett., vol. 15, no. 5, p. 160, 1994.
[5.9]. S. Hasegawa ,S. Sakamoto, T. Inokuma, and Y. Kurata “structure of recrystal silicon films prepared from amorphous silicon deposited using disilane.” Appl. Phys.Lett. 62(11),15 March 1993.
[5.10]. E. G. Lee,J. J. Kim “Investigation of microstructure and grain grownth of polycrystalline silicon deposited using silane and disilane.” Thin Solid Films . 226(1993)123-128.
Chapter 6
[6.1]. Roberto Versari, Augusto Pieracci, Damiana Morigi, and Bruno Ricco. “ Fast Tunneling Programming Memories” , IEEE Trans. On Electron Device, vol. 47, NO. 6, JUNE 2000.
[6.2].Runnion, E.F.; Gladstone, S.M., IV; Scott, R.S.; Dumin, D.J.; Lie, L.; Mitros, “Limitations on oxide thicknesses in flash EEPROM applications”, J. Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International , 1996
Page(s): 93 —99
[6.3]. Lai, S., “Tunnel oxide and ETOX/sup TM/ flash scaling limitation “, Nonvolatile Memory Technology Conference, 1998 Proceedings. Seventh Biennial IEEE , 1998 Page(s): 6 —7
[6.4].Ushiyama, M.; Satoh A.; Kume H., “Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory”, Symposium on VLSI Technology, 1999. Digest of Technical Papers. , 1999 Page(s): 23 —24
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[6.7]Buller, J.F.; Bandyopadhyay, B.; Garg, S.; Patel, N. “Improved EEPROM tunnel- and gate-oxide quality by integration of a low-temperature pre-tunnel-oxide RCA SC-1 clean”, IEEE Trans. on Semiconductor Manufacturing, Volume: 9 Issue: 3 , Aug. 1996 Page(s): 471 —476
[6.8].Ghidini, G.; Drera, D.; Maugain, F., “F contamination effects on intrinsic and extrinsic gate oxide reliability“, Integrated Reliability Workshop, 1995. Final Report., International , 1995 Page(s): 92 —97
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[6.11].Balasinski, A.; Vishnubhotla, L.; Ma, T.P.; Tseng, H.-H.; Tobin, P.J. ,“Fluorinated CMOSFETs fabricated on (100) and (111) Si substrates“, VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers.1993 International Symposium on , 1993 Page(s): 95 —99
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Chapter 7
[7.1] T. Fuyuki, S. Murakawa, and H. Matsunami, “Initial stage of ultra-thin SiO2 formation at low temperatures using activated oxygen”, Appl. Surf. Sci. Vol. 117/118, 1997, p.123.
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[7.3] M. Hirayama, K. Sekine, Y. Saito, and T. Ohmi, “ Low- Temperature Growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High-Density Krypton Plasma,” IEDM 99, p.249
[7.4]Y. Shi, X. Wang, and T. P. Ma, “ Electrical Properties of High-Quality Ultrathin Nitride/ Oxide Stack Dielectrics” IEEE TRANS. ON ELECTRON DEVICES, VOL. 46, NO 2, FEB. 1999
[7.5].C.G. Parker, G. Lucovsky, and J. R. Hauser, “ Ultra-thin Oxide-Nitride Gate Dielectric MOSFET’s” IEEE ELECTRON DEVICE Lett. VOL. 19. NO. 4 APRIL 1998.
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