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研究生:陳東暘
研究生(外文):Tung-Yang Chen
論文名稱:基體觸發技術與積體電路晶片上之靜電放電防護電路設計
論文名稱(外文):SUBSTRATE-TRIGGERED TECHNIQUE FOR ON-CHIP ESD PROTECTION DESIGN IN DEEP-SUBMICRON CMOS INTEGRATED CIRCUITS
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou Ker
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:210
中文關鍵詞:靜電放電基體觸發技術閘極驅動技術類比電路靜電放電防護設計複晶矽二極體
外文關鍵詞:ESDSubstrate-Triggered TechniqueGate-Driven TechniqueAnalog ESD Protection Circuit DesignPolysilicon Diode
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本論文提出基體觸發技術在靜電放電下啟動的物理機制,並將其應用在深次微米互補式金氧半積體電路(deep-submicron CMOS IC)的靜電放電防護設計上,因應積體電路中不同的需求,而設計出各種靜電放電防護電路,以避免積體電路受到靜電放電的破壞。由於在先進的製程中,半導體元件的接面崩潰(Junction Breakdown)電壓越來越接近閘極氧化層(Gate Oxide)的崩潰電壓,在靜電放電(ElectroStatic Discharge, ESD)防護的設計上,傳統的設計方法已越來越加困難。閘極驅動(Gate Driven)技術以及基體觸發(Substrate Triggered)技術都是為了提昇靜電放電防護元件在靜電放電衝擊時的反應效率及防護能力,所發展出的最新技術。但是在進入深次微米的製程時,閘極驅動技術也越來越難以設計及控制,從本論文的研究中證實基體觸發技術對於靜電放電防護的設計是一個最佳最有效的方法。
首先,從靜電放電防護基本元件在遭到靜電放電衝擊下啟動的基本原理為起點,實際在0.35微米製程中,以變化不同的佈局參數,來改變指狀結構(Finger type)靜電放電防護基本元件的佈局結構,以靜電放電實驗及二次崩潰點(Secondary Breakdown)的量測來說明元件結構對靜電放電耐受力的影響,並由靜電放電防的測試結果中,求得最佳佈局方式,再從靜電放電防護元件之能帶圖(Energy Band Diagram)變化與觀察其在發射顯微鏡(EMission MIcroscope, EMMI)下的啟動變化分析,更進而說明元件在受到靜電放電衝擊下的啟動原理,並做一詳盡的物理定性分析,進而了解佈局參數對靜電放電防護能力影響的物理因素。從了解基本元件在遭到靜電放電衝擊下啟動的基本原理後,進一步分析閘極驅動技術及基體觸發技術的動作原理以及其對靜電放電防護的特性。由利用實驗設計的技巧,觀察其在發射顯微鏡下受到閘極驅動及基體觸發的啟動變化,並借由靜電放電防護元件之能帶圖的變化進行比對分析,再以靜電放電實驗及二次崩潰點的量測分析,分別在0.18及0.35微米互補式金氧半製程中,用相同的實驗設計,均證實閘極驅動技術在高驅動電壓下,會對元件的靜電放電能力造成不良之影響,而對基體觸發技術而言,高觸發電流對元件的靜電放電能力卻有正面的影響。因此從閘極驅動技術及基體觸發技術不同的啟動機制實驗分析,得到基體觸發技術確實更能適用在深次微米的互補式金氧半積體電路中。
在積體電路中需要有全面性靜電放電防護設計(Full ESD Protection Design)的觀點是越來越重要,對於先進的積體電路,無論在輸入、輸出極甚至電源間皆必需有完整的靜電放電防護設計,在本論文中,將基體觸發技術實際應用在0.18微米互補式金氧半製程中,發展出一套基體觸發靜電放電防護電路,分別應用在輸入、輸出極以及電源VDD與VSS間,同時也在相同的製程中,製作傳統的靜電放電防護電路以做為比較。從人體模式(Human Body Model, HBM)的靜電放電測試中發現,在本製程中對靜電放電防護能力原本相當不理想的輸出極(W/L = 300µm/0.3µm),在加入基體觸發技術的輸出保護電路後,可從原來0.65 kV的靜電放電耐受力增加到3.2 kV,證實了基體觸發技術的實用性。此外,在先進的深次微米製程中,由於元件的結構等比例地縮小,因此使用的電源電壓也必需從傳統的5伏特降下到3.3伏特甚至是1.8伏特,因此電子系統也必需混合5伏特及3.3伏特的電源電壓,例如一個3.3伏特電壓源的積體電路之輸入端,就可能必需接到一個5伏特的輸入訊號,因此在此種輸入端的靜電放電防護設計,就必需有特殊的考量。在本論文中,提供了一種新式且不需額外加遮蔽金屬矽化物的光罩(Salicide Blocking Mask)及專為靜電放電防護佈植(ESD implantation)的輸入極靜電放電防護電路,應用在這種混合電壓之電路的輸入極當靜電放電保護電路。在適當的佈局下,整個電路可以整合在一個單一的矽元件結構中,以加強其基體觸發的能力。在本論文中,此種設計也實際在0.25微米互補式金氧半的製程中製作出來,其中150 微米總寬度的此種新式元件,在人體模式的靜電放電測試下,可以有效改善沒有基體觸發之基本元件的靜電放電耐受能力,在單位面積的比較下,實驗結果顯示其靜電放電耐受能力可以從原來的1.2 V/µm2增加到1.73 V/µm2。
而在電源間的靜電放電箝制電路方面,本論文除了在0.18微米製程中所設計的基體觸發電路外,本論文還在0.6微米互補式金氧半製程中提出四種新式的基體觸發靜電放電箝制元件,而為了使靜電放電電流能夠更均勻,這些靜電放電箝制元件被設計成多單元的四方形結構,並將其設計應用在靜電放電箝制電路中。這些靜電放電箝制元件是直接利用到互補式金氧半元件中具有寄生雙載子電晶體的特性,而將基體觸發的原理應用這些元件上,使其在靜電放電時能夠迅速而均勻地開啟。這些元件包含了:基體觸發水平雙載子電晶體(STLB),基體觸發垂直雙載子電晶體(STVB),基體觸發雙雙載子電晶體(STDB),以及雙極觸發雙雙載子電晶體(DTDB)。在電路的設計方面,一種以電阻-電容為基礎的靜電放電偵測電路被用來做為主要的電路,以產生觸發電流來快速而有效地驅動這些靜電放電箝制元件。由靜電放電測試實驗結果顯示,具有基體觸發雙雙載子電晶體(STDB)的基體觸發之源極間的靜電放電箝制電路,可以比傳統閘極驅動之靜電放電箝制電路在同樣的箝制元件面積下改善200%。
由於在類比電路中,積體電路的輸入電容不可太大,而且必需對輸入訊號的變化能有一穩定值,但為承受理想的靜電放電耐受能力,靜電放電防護元件通常具有較大的接面電容值,而且對電壓的變化又相當敏感。因此,在對元件啟動的特性了解後,本論文亦提出在類比電路中設計靜電放電防護電路的解決方案。由此設計理念,在0.35微米金氧半製程中,可以設計出50微米/0.5微米大小的輸入/輸出極,使得整個輸入電容降到只有~0.4pF,而在人體模式及機械模式(Machine Model)的靜電放電防護測試下分別可以得到6 kV及400 V的靜電放電耐受力。在本論文中,更對此設計方式做一深入的探討,而提出一整套完整的設計方法來適用在所有類比電路的輸入/輸出設計中,使得輸入電容在隨1 V工作電壓變化範圍下能控制在1%的誤差內。
此外,由於二極體可以在積體電路的靜電放電防護之設計上廣泛應用,但由於傳統二極體在積體電路中會形成寄生的雙載子電晶體,因此在實際應用時會有難以控制的漏電電流的產生,在本論文中也首先提出利用複晶矽二極體(Polysilicon Diode)應用到積體電路的靜電放電防護設計上,由此可以設計出全面性的靜電放電防護電路,而利用堆疊的複晶矽二極體當靜電放電控制電路的方法,也設計出一個在設計電路時可以有效控制漏電電流的電源間靜電放電箝制電路。在本論文中,對複晶矽二極體的雜質摻雜濃度以及一些佈局參數的變化對其特性及靜電放電耐受能力的影響,也做了詳細的分析。此外,利用堆疊的複晶矽二極體亦可設計出一種新式具有低漏電電流的電源間靜電放電箝制電路,此種電路在整個積體電路設計之初,即可事先模擬及安排,有效控制其在電源間的漏電電流。本論文將這些元件及電路實際應用到智慧卡(Smart Card)中,由整體的靜電放電防護設計下,可以成功地將原來只有300 V之人體模式靜電放電耐受力的產品,改善到大於3 kV。

This thesis includes physical analysis for the turn-on mechanisms of ESD protection devices during ESD stress and the applications of on-chip substrate-triggered ESD protection design. Gate-driven and substrate-triggered technologies are used to improve the turn-on efficiency of ESD (ElectroStatic Discharge) protection devices. From the analysis of the turn-on mechanisms of ESD protection device with gate-driven and substrate-triggered design in this thesis, it is proved that the substrate-triggered ESD protection design can continually improve the ESD robustness of protection devices in deep-submicron CMOS process. But, the gate-driven design has been confirmed to cause a sudden degradation on ESD robustness of the ESD protection devices. By using the substrate-triggered technique, the input, output, and power-rail ESD protection circuits are developed to enhance the ESD robustness of integrated circuits in deep-submicron CMOS process.
To understand the turn-on mechanisms of ESD protection device during ESD stress, the turn-on characteristics of those devices must be measured and analyzed. The energy band diagrams, EMMI (EMission MIcroscope) photographs, and TLP (Transmission Line Pulsing) measurement have been used to analyze and explain the physical turn-on mechanisms of ESD protection device. From the investigation of layout dependence on ESD robustness of NMOS and PMOS with finger-type layout, the turn-on mechanisms of ESD protection devices can be clearly understood to optimize the layout rules for the device dimensions, layout spacings, and clearances of those devices. To design high performance ESD protection device, some layout parameters must be optimized. The optimized layout parameters for a 0.35-µm CMOS process have been clearly investigated and analyzed in this thesis. To improve the ESD robustness of protection devices, gate-driven and substrate-triggered techniques have been developed. The gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices are also measured and compared in this thesis. The operation principles of gate-driven design and substrate-triggered design for ESD protection can be explained clearly by energy band diagrams and EMMI photographs. The experimental results have confirmed that the substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices than the gate-driven design. But, the gate-driven design cannot continually improve ESD level of the device in the same deep-submicron CMOS process.
Full ESD protection design has became an important issue for integrated circuits in advanced deep-submicron CMOS process. To effectively improve ESD (electrostatic discharge) robustness of IC products, a novel substrate-triggered design for input, output, and power-rail ESD protection, as comparing to the traditional gate-driven technique, has been proposed in this thesis. With the substrate-triggered technique, the novel on-chip ESD protection circuits for the input, output, and power pins have been designed and verified in a 0.18-µm CMOS process. The HBM ESD robustness of output ESD protection circuits with ESD protection NMOS of W/L = 300µm/0.3µm can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV by the proposed substrate-triggered design. With aggressive device scaling, the circuit operating voltage had been decreased correspondingly. Some early 5-V systems changed from 5 V to 3.3 V, or even 1.8 V. Thus, system voltages were no longer 5 V but mixed with 5 V and 3.3 V. For mixed-voltage input design, the IC with 3.3-V power supply needs to accept 5-V input signals. A substrate-triggered technique is proposed to improve ESD protection efficiency of the ESD protection circuit without extra salicide-blocking and ESD-implantation process modifications in a salicided shallow-trench isolation (STI) CMOS process. By using layout technique, the proposed input ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase the ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered input ESD protection circuit with a field oxide device of channel width of 150 µm can sustain a HBM (Human-Body-Model) ESD level of 3250V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded NMOS (gg-NMOS) with salicide-blocking process modification in a 0.25-µm salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve the ESD robustness per unit silicon area from the original 1.2 V/µm2 of gg-NMOS to 1.73 V/µm2.
Four novel ESD clamp devices for using in power-rail ESD clamp circuits with the substrate-triggered technique are proposed to improve ESD level in this thesis. The parasitic n-p-n and p-n-p bipolar junction transistors (BJT) in the CMOS devices are used to form the substrate-triggered devices for ESD protection. Four substrate-triggered devices are proposed and investigated in this work, which are named as the substrate-triggered lateral BJT (STLB), the substrate-triggered vertical BJT (STVB), the substrate-triggered double BJT (STDB), and the double-triggered double BJT (DTDB). An RC-based ESD-detection circuit is used to generate the triggering current to turn on the proposed substrate-triggered devices. In order to trigger on the parasitic bipolar transistors more effectively, the symmetric multiple-cell square-type layout method is used to realize these substrate-triggered devices. The power-rail ESD clamp circuits with such substrate-triggered devices have been fabricated in a 0.6-µm CMOS process. Experimental results have shown that the substrate-triggered device with double-BJT structure can provide 200% higher ESD robustness in per silicon area, as compared to the NMOS with the traditional gate-driven design.
To keep the total input capacitance almost constant for analog IC design, a design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for high-frequency applications. The device dimension (W/L) of ESD protection device connected to the I/O pad can be reduced to only 50m/0.5m in a 0.35-m silicided CMOS process, but it can sustain HBM (MM) ESD level up to 6kV (400V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~0.4pF for high-frequency applications. This input capacitance can be further reduced if the ESD protection devices are designed with smaller device dimensions. Moreover, by using the optimized layout design to draw the layout of ESD protection NMOS and PMOS devices, the voltage-dependent variation on input capacitance of this analog ESD protection circuit can be kept below 1% under an input voltage swing of 1V. With such almost constant input capacitance, the nonlinear distortion causing by on-chip ESD protection circuit can be minimized for high-precision applications.
A novel on-chip ESD protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this work. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart card IC’s. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulsing (TLP) generator to investigate its ESD robustness. Moreover, by adding a new power-rail ESD clamp circuit with the stacked polysilicon diodes as the turn-on control circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300V to become ≥ 3kV. This design has been practically applied in a mass-production smart card IC.

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) iv
ACKNOWLEDGEMENTS viii
CONTENTS
TABLE CAPTIONS
FIGURE CAPTIONS
CHAPTER 1 INTRODUCTION
1.1 BACKGROUND
1.2 ESD TESTING COMBINATION ON IC
1.3 THESIS ORGANIZATIONTABLES
FIGURES
CHAPTER 2 DEPENDENCE OF LAYOUT PARAMETERS ON ESD ROBUSTNESS OF CMOS DEVICES
2.1 TURN-ON MECHANISM OF MOSFET UNDER ESD STRESS
2.2 LAYOUT DEPENDENCE
2.2.1 Channel Width and Silicide Effect
2.2.2 Channel Length
2.2.3 Clearance from Drain/Source Contact to Poly-Gate Edge
2.2.4 Spacing from Drain Diffusion to Guardring Diffusion
2.2.5 Unit-Finger Width
2.3 SUMMARYTABLESFIGURES
CHAPTER 3 GATE-DRIVEN EFFECT VERSUS SUBSTRATE-TRIGGERED EFFECT
3.1 GATE-DRIVEN EFFECT
3.1.1 Turn-on Mechanism of Gate-Driven Design
3.1.2 Experimental Results
3.2 SUBSTRATE-TRIGGERED EFFECT
3.2.1 Turn-on Mechanism of Substrate-Triggered Design
3.2.2 Experimental Results
3.3 SUMMARY
FIGURES
CHAPTER 4 ON-CHIP ESD PROTECTION CIRCUITS DESIGN BY USING SUBSTRATE-TRIGGERED TECHNIQUE
4.1 SUBSTRATE-TRIGGERED ESD PROTECTION DEVICE
4.1.1 Device Structure
4.1.2 Device Characteristics
4.2 ESD PROTECTION CIRCUITS WITH SUBSTRATE-TRIGGERED DESIGN
4.2.1 Input ESD Protection Circuits
4.2.2 Output ESD Protection Circuit
4.2.3 Power-Rail ESD Clamp Circuit
4.3 EXPERIMENTAL RESULTS
4.3.1 HBM ESD test Results
4.3.2 Turn-on Verification
4.4 SUMMARY
FIGURES
CHAPTER 5 SUBSTRATE-TRIGGERED ESD PROTECTION CIRCUIT WITHOUT EXTRA PROCESS MODIFICATION
5.1 SUBSTRATE-TRIGGERED ESD PROTECTION CIRCUIT
5.1.1 The Substrate-triggered Input ESD Protection Circuit
5.1.2 Alternative Substrate-triggered Input ESD Protection Circuit
5.1.3 Realization of Substrate-Triggered ESD Protection Circuits
5.2 EXPERIMENTAL RESULTS
5.2.1 Device Characteristics
5.2.2 TLP Measurement
5.2.3 ESD Test
5.3 MODIFIED DESIGN WITH ENHANCED TURN-ON SPEED
5.4 SUMMARY
FIGURES
CHAPTER 6 POWER-RAIL ESD CLAMP CIRCUITS WITH SUBSTRATE- TRIGGERED TECHNIQUE
6.1 SUBSTRATE-TRIGGERED ESD CLAMP DEVICES
6.1.1 Substrate-Triggered Lateral BJT (STLB) Device
6.1.2 Substrate-Triggered Vertical BJT (STVB) Device
6.1.3 Substrate-Triggered Double BJT (STDB) Device
6.1.4 Double-Triggered Double BJT (DTDB) Device
6.2 CIRCUIT SIMULATION
6.2.1 ESD Stress Condition
6.2.2 VDD Power-on Condition
6.3 EXPERIMENTAL RESULTS
6.3.1 Device Characteristics
6.3.2 ESD Performance and TLPG I-V Curves
6.3.3 Turn-On Verification
6.3.4 Power-Rail Noise Clamping
6.4 SUMMARY
FIGURES
CHAPTER 7 ANALOG ESD PROTECTION CIRCUIT WITH LOW INPUT CAPACITANCE FOR HIGH-FREQUENCY APPLICATIONS
7.1 ANALOG ESD PROTECTION CIRCUIT
7.2 LAYOUT DESIGN ON THE INPUT CAPACITANCE
7.2.1 Calculation on the Input Capacitance
7.2.2 Layout Design to Minimize Capacitance Variation
7.2.3 Calculation Results
7.3 SUMMARY
TABLES
FIGURES
CHAPTER 8 ON-CHIP ESD PROTECTION DESIGN BY USING POLYSILICON DIODES IN CMOS PROCESS
8.1 ORIGINAL DESIGN IN A SMART CARD IC
8.2 NEW ON-CHIP ESD PROTECTION DESIGN
8.2.1 ESD Protection Circuit
8.2.2 Leakage Current in the VDD-to-VSS ESD Clamp Circuit
8.2.3 Process Splits
8.3 DEPENDENCE OF LAYOUT PARAMETERS ON It2 OF POLYSILICON DIODES
8.4 EXPERIMENTAL RESULTS AND DISCUSSION
8.4.1 ESD Test and Failure Analysis
8.4.2 Turn-on Verification
8.5 SUMMARY
8.6 APPENDIX
TABLES
FIGURES
CHAPTER 9 CONCLUSIONS AND FUTURE WORKS
9.1 MAIN RESULTS OF THIS THESIS
9.2 FUTURE WORKS
TABLES
REFERENCES
VITA
PUBLICATION LIST

[1] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, Wiley, 1995.
[2] J. E. Vinson and J. J. Liou, “ESD protection techniques for semiconductor devices,” in Proc. of Int. Conf. on Microelectronic, 2000, pp. 311-321.
[3] MIL-STD-883E method 3015.7, Military Standard Test Methods and Proc. for Microelectronics, Dept. of Defense, Washington D.C., U.S.A., 1996.
[4] Electrostatic Discharge (ESD) Sensitivity Testing — Human Body Model (HBM), test method A114-A, EIA/JEDEC Standard, Electronic Industries Association, 1997.
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