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研究生:鄭念祖
研究生(外文):Cheng Nean Chu
論文名稱:深次微米元件之低頻雜訊分析
論文名稱(外文):Investigation of Low Frequency Noise in Deep-Submicron MOSFET
指導教授:汪大暉
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:50
中文關鍵詞:雜訊退化前端製程
外文關鍵詞:Low Frequency NoiseDegradationFront-end Process
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  • 被引用被引用:0
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在類比電路應用中,降低雜訊為一項重要議題,也限制了訊號的精確度和可測性;而隨著射頻積體電路的需求日益增長,使深次微米元件之低頻雜訊研究更形迫切,主要乃因低頻雜訊將倍頻而影響非線性電路及元件之高頻相位雜訊。此外,雜訊受製程技術影響深遠,故可用以了解元件特性並預測其衰退機制。
本篇即以 Unified Noise Model 為基礎,探究元件低頻雜訊的來源,討論各項相關議題。首先,研究元件微縮對雜訊之影響,了解元件雜訊變異及載子分佈N(y)、通道長度L與雜訊之關係,此外,將介紹利用低頻雜訊量測萃取元件spacer下之缺陷密度的方法。其次,探討不同退化機制對雜訊之變化情形,確立不規則的臨界電壓VT將導致雜訊增加。最後,略述深次微米元件中一些特殊先進製程步驟對雜訊之效應,並介紹可降低雜訊之製程。

Interest in low-frequency noise behavior of deep-submicron Si MOSFETs is first of all drawn by analog applications, where noise minimization is a key issue in circuit sensitivity and detection. Nowadays, low frequency noise receives growing attention from RF community as well. The reason is that low-frequency noise potentially has an impact on the phase noise of nonlinear circuits and devices in the GHz regime. The third motivation for this study is that noise is a sensitive technology parameter, which can be used as a predictive or a diagnostic tool for the durability and reliability of a device.
The main theme of this work will focus on the origin of noise in MOSFETs. Based on the unified flicker noise model, several issues will be addressed. Firstly, the impact of device scaling on flicker noise will be investigated. Carrier distribution and channel length dependence of noise behavior will be discussed. Furthermore, we will introduce a 1/f noise technique to extract oxide trap density in the spacer region of a MOSFET. Secondly, attention will be paid to the correlation between different stress modes with flicker noise degradation. It was observed that the non-uniform distribution of threshold voltage along the channel has a large effect on noise degradation. Finally, the dependence of noise on device processing steps will be studied. Guidelines for low-noise processing will be recommended.

Chinese Abstract i
English Abstract ii
Acknowledgements iii
Contents iv
Figure Captions v
Chapter 1  Introduction 1
Chapter 2  Basic Noise Theory 3
     2.1 Introduction 3
    2.2 What is Noise 3
    2.3 Mathematical Methods 3
2.4 Flicker Noise Model 7
Chapter 3  Device Scaling Effects on Flicker Noise 12
     3.1 Introduction 12
3.2 Experimental Setup 12
    3.3 Noise Characterization 14
3.4 Carrier Distribution Dependence
of Flicker Noise 18
3.5 Channel Length Dependence
of Flicker Noise 22
3.6 Interface State Characterization
by Using Flicker Noise 23
Chapter 4  Stress Effects on Flicker Noise 27
    4.1 Introduction 27
    4.2 Maximum Substrate Current Stress 27
4.3 Maximum Gate Current Stress 33
4.4 Fowler-Nordheim Stress 33
4.5 Non-Uniform Threshold Voltage
Enhance Noise Degradation 37
Chapter 5  Advanced Front-end Process
Effects on Flicker Noise 40
     5.1 Introduction 40
    5.2 Gate Oxidation 40
5.3 Well Formation 41
5.4 Guidelines for Low-Noise CMOS Technology 44
Reference 46

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