跳到主要內容

臺灣博碩士論文加值系統

(35.153.100.128) 您好!臺灣時間:2022/01/19 04:02
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:丁子仁
論文名稱:一種低功率靜態隨機存取記憶體的電流模式感測放大器
論文名稱(外文):A Current-Mode Sense Amplifier for Low Power SRAM
指導教授:吳慶源
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:靜態隨機存取記憶體
外文關鍵詞:SRAM
相關次數:
  • 被引用被引用:0
  • 點閱點閱:174
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
高速且低功率的靜態存取記憶體是許多超大型積體電路中的關鍵性零組件,如何減少工作時的功率及待命狀態的直流電流與漏電流是設計時的重點。為了減少讀寫操作時所消耗的功率,同時不影響讀寫的速度,本論文提出一種低操作功率且高速的讀寫模式。這種新的讀寫電路在讀出與更新資料時只需改變少許的位元線的電壓。在讀取資料時,此一模式可以減少功率消耗並且快速的讀出記憶細胞內的資料;資料由外寫入時,可以減少位元線與資料之驅動器的功率消耗。除了新讀寫模式的應用外,還有其他設計方法可以減少功率消耗。以128Kx8 SRAM 為例,記憶體可分成四個區塊,使得工作功率的消耗減少為原來的四分之一;降低工作電壓,使消耗的功率隨電壓變化幅度的減少而下降;使用脈波字線的技術,可以減少在做位元線平衡時所消耗的功率,並增加記憶細胞的穩定性。藉由上述的設計方式能夠達到低功率及高速的記憶體晶片設計。

Chapter 1 Introduction
Chapter 2 Low-Power Circuit Techniques in SRAM
2.1 Internal Supply Voltage
2.2 SRAM Partitioning
2.3 Address Transition Detection for Pulsed Word-Line technique
Chapter 3 Low-Power and High-Speed Read Circuit with Current-
Mode Sense Amplifier
3.1 Voltage-Mode Signal Delay versus Current-Mode Signal Delay
3.2 Clamped Bit-Line Sense Amplifier ( CBLSA )
3.3 Hybrid Sense Amplifier
3.4 A New Current-Mode Sense Amplifier
3.5 Simulation Results
Chapter 4 Low Operation Power and High-Speed Write Method
4.1 Conventional Voltage-Writing Mechanism
4.2 A New Current Writing Mechanism
4.3 Simulation Results
Chapter 5 128 K x 8 SRAM Circuit Design
5.1 The Whole Architecture of Memory
5.2 Circuits in Top Section
5.3 Circuits in Bottom Section
5.4 R&W Switch
5.5 The C_B Section
5.6 Pre-decoder and Decoder
5.7 Memory Cell
5.8 Simulation Results
Chapter 6 Conclusions

[1]K. Itoh, K. Sasaki, and Y. Nakagome, “ Trends in Low-Power RAM Circuit Technologies “ Dig. Tech. Papers, 1994 Symp. Low Power Electronics, 1994 pp.84-87.
[2]M. Yoshimoto, et, al. “ A 64kb CMOS RAM with divided word line structure “ IEEE International Solid State Circuits Conference, Digest of Technical Papers, pp.58-59, 1983.
[3]Minato, O et, al. “ A 20ns 64k CNOS static RAM “IEEE Journal of Solid-State Circuits Vol. SC-19, No.5 pp.1008 December 1984
[4]H. Lee and G. E. Sobelman “ New Low-Voltage Circuits for XOR and XNOR “ IEEE Proceedings of Southeastcon '97. Engineering new New Century, pp.225-229, 1997
[5]E. Sccvinck, P. J. van Beers, and H. Ontrop, “ Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM’s, “ IEEE Journal of Solid-State Circuits Vol.26 No.4 pp.525-536 April 1991
[6]T. N. Blalock and R. C. Jaeger, “ A High-Speed Sensing Scheme for 1T Dynamic RAM’s Utilizing the Clamped Bit-Line Sense Amplifier, “ IEEE Journal of Solid-State Circuits Vol.27 No.4 pp.618-625 April 1992
[7]P.Y. Chee, P.C. Liu, and L. Siek, “ High-Speed Hybrid Current-Mode Sense Amplifier for CMOS SRAMs, “ Electronics Letters 23rd Vol.38 No.9 pp.871-873, April 1992
[8]J. Alowersson and P. Andersson, “ SRAM Cells for Low-Power Write in Buffer Memories, ” Low Power Electronics, 1995., IEEE Symposium on 1995 pp. 60—61
[9]J. S. Wang, W. Tseng, and H. Y. Li, “ Low-Power Embedded SRAM with the Current-Mode Write Technique, “ IEEE Journal of Solid-State Circuits, Vol.SC-35, No.1, pp.119-124, January 2000
[10]E. Seevinck, F.J. List, and J. Lohstroh, “ Staitic-Noise Margin Analysis of MOS SRAM Cells, “ IEEE Journal of Solid-State Circuits, Vol. SC-22, pp.748-754, Oct. 1987
[11]D.H. Wang “ A Current-Mode Read/ Write Circuit for Low Operation Power/High Speed SRAM and Its Application in SRAM Chip Implementation ” 2000 Master thesis, Institute of Electronics, National Chiao-Tung University.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top