複晶矽薄膜電晶體已經廣泛的使用在液晶顯示器中的畫素控制元件，而將驅動電路整合在同一玻璃基板上是未來的趨勢。對於驅動電路工作來說，不同於畫素控制元件，它必須有高的驅動電流和低的關閉態漏電流。已經有很多種提升驅動電流技術提出，但如此一來關閉態漏電流也相對的大增。所以本篇論文提出了一種具有浮動副閘極新穎的薄膜電晶體結構。當元件工作在關閉態時，就會像偏移結構的元件一樣的關閉態特性，而當元件工作在開啟態時，會和傳統元件一樣的開啟態特性。新結構的開啟態漏電流會比傳統元件的漏電流低上兩個數量級以上，而其開啟態電流會比偏移結構元件高一個數量級以上。因為此結構可以降低在關閉態時汲極附近的電場，而在開啟態時可經由浮動閘極的耦合不使電場降低太多。總和來說，在元件的開關電流比可以增加兩個數量級以上，且在製作此新結構元件不需要增加多餘的光罩，和傳統結構的四道光罩相同。

Polysilicon thin film transistor (poly-Si TFT) has been used widely as the pixel switching devices in Active-Matrix Liquid Crystal Displays (AMLCD). It’s said that system on panel (SOP) that integrates all driving circuits on the glass is the tendency in the future. For circuit operation, distinct switching device, it must have low leakage current and high on state current. Various techniques have been reported to raise the driving current but the leakage current also increases at the same time. So we propose a novel poly-Si TFT with a floating subgate structure in this thesis. The device operates as an offset gated structure in the OFF state, while acting as a conventional non-offset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional non-offset TFT, and the ON current of the new TFT is one order of magnitude higher than that of the offset TFT. With these novel TFTs structures, we can effectively reduce off-state leakage current resulting mainly from a higher electric field near the drain and the turn-on current will not be degraded. The ON / OFF current ratio of the new TFT is greatly improved by two orders of magnitude. Beside, no additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional non-offset TFTs.

Contents
Chinese Abstract…………………………………………………………i
English Abstract………………………………………………………ii
Acknowledgements……………………………………………………iv
Contents…………………………………………………………………v
Figure and Table Captions………………………………………………vi
Chapter 1 Introduction………………………………………………1
1.1 Background and Motivation……………………………………1
1.2 Thesis Outline…………………………………………………3
1.3 Reference………………………………………………………4
Chapter 2 Experimental and Device Innovation………………………9
2.1 Poly-Si TFT Fabrication Process…………………………9
2.2 The Principle of Proposed Device…………………………10
2.3 Experiment split condition…………………………………12
2.4 Reference……………………………………………………13
Chapter 3 Discussion and Result………………………………………14
3.1 Medic Simulation……………………………………………14
3.2 NH3 Passivation Treatment…………………………………15
3.3 Effect of Coupling Ratio……………………………………16
3.4 Reference……………………………………………………19
Chapter 4 Conclusion and Future Work………………………………20

[1.1] C. H. Fa and T. T. Jew, “The polysilicon insulated-gate field-effect transistors,” IEEE Trans. Electron Devices, vol. 13, no. 2, p.290, 1966.
[1.2] T. I. Kamins, “Hall mobility in chemically deposited polycrystalline silicon,” J.Appl. Phys., vol. 42, p. 4357, 1971.
[1.3] J. Y. W. Seco, “The electrical properties of polycrystalline silicon films,” J. Appl. Phys.,vol. 46, p. 5274, 1975.
[1.4] S.Morozumi et al., SID Digest, p. 156, 1983.
[1.5] S.Morozumi, H. Kurihara, T. Takeshita, H. Oka, and K, Hasegawa,
“Completely integrated contact-type linear image sensor,” IEEE Tans. Electron Devices, vol 32, no. 8, p. 1546, 1985.
[1.6] Y. Hayashi, H. Hayashi, M. Negishi, T. Matusushita, M. Yagino, and T. Endo, ”A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chip,” in ISSCC Digest, p. 266, 1988.
[1.7] F. Okumura et al., in IDRC Digest, P. 174, 1988.
[1.8] N. Yamauchi, Y. Inaba, and M. Okamura, “An integrated photodector-amplifier using a-Si p-I-n photodiodes and poly-Si thin-film transistors,” IEEE Photonic TECH. Lett., vol. 5, no. 3, p. 319, 1993.
[1.9] S. D. S. Malhi, H. Shichijo, S. K. Ganerjee, R. Sundaresan, M. Elehy, G. P. Pollack, W. F. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P. K. Chatterjee, and H.W. Lam, TEEE Trans. Electron Devices, vol. 32, p. 258, 1985.
[1.10] M. Kinugawa M. Kakumu, T. Yoshida, T. Nagayama, S. Morita, K, Kubota, F. Matsuoka, H. Oyamatus, K. Ochii, and K. Maeguchi, “TFT cell technology for 4 Mbit and more high density SRAMs,” 1990 Symp. on VLSI Tech., p. 23.
[1.11] S. koyama, “ A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin-film transistors,” in 1992 Symp. On VLSI Tech, p. 44.
[1.12] N. D. Toung, G.Harkin, R. M. bunn, D.J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process, “ IEEE Trans. Electron Devices, vol. 43, no. 11, p 1930, 1996.
[1.13] J.Ohwada, M. Takabatake, Y. A. Ono, A. Mimura, K. Ono and N. Konish, ”Perpheral circuit integrated poly-Si TFT LCD with gray scale representation,” IEEE Trans. Electron Devices, vol. 36, no. 9, p. 1923, 1989.
[1.14] A. G. Lewis, David D.Lee, and R. H. Bruce, “Polysilicon TFT circuit design and performance,” IEEE J. Solid-State Circuits, vol. 27, no. 12, p. 1833, 1992.
[1.15] T. Morita, Y. Yamamoto, M, Itoh, H. Yoneda, Y.Yamane, S. Tsuchimoto, F. Funada, and K. Awane, “ VGA driving with low temperature processed poly-Si TFTs,” in IEDM TECH. Dig. 1995, p. 841.
[1.16] M. J. Edwards, S. D. Brotherton, J. R. Ayres, D. J. McCulloch, and J. P. Gowers, “Laser crystallized poly-Si circuits for AMLCDs,” Asia Display, p. 335,1995.
[1.17] T. Yamanaka et al., “ A 25 mm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity,” in IEDM Tech. Dig. 1988, p. 48.
[1.18] I. Naiki et al., “ Center word-line cell: a new symmetric layout cell for 64Mb SRAM,” in IEDM Tech. Dig. 1993, p. 817.
[1.19] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si,” IEE proc. Circuits Decices Syst., vol. 141, no. 1, p. 38, 1994.
[1.20] M. J. Powell , C. van Derkel, and J. R. Hughes, “ Time and temperature dependence of instability mechanisms in amorphous silicon TFTs,” Appl. Phys. Lett., vol. 54, no. 14, p. 1323, 1989.
[1.21] R. B. Inverson et al., “Recrystallization of amorphized polycrystalline silicon films on silicon dioxide：Temperature dependence of the crystallization parameters”, J. Appl. Phys. , Vol. 62, p.1675, 1987.
[1.22] M. K. Hatalis et al., “Large grain polycrystalline silicon by low temperature annealing of low pressure chemical vapor depositied amorphous silicon film”, J. Appl. Phys. , Vol. 63, p.2260, 1988.
[1.23] K. Shimizu et al., “High mobility Poly-Si thin-film transistors fabricated by a novel excimer laser c rystallization method”, IEEE Trans. Electron Devices, Vol. 40, p.112, 1993.
[1.24] S.D. Brotherton et al., “Excimer laser annealed Poly-Si thin-film transistors”, IEEE Trans. Electron Devices, Vol. 40, p.407, 1993.
[1.25] Man Wong et al., “High performance low temperature metal induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel application”, IEEE Trans. Electron Devices, Vol. 47, no.2, 2000.
[1.26] Seung-Ki Joo et al., “ Fabrication of high mobility p-channel Poly-Si thin film transistors by self-aligned metal indiced lateral crystallization”, IEEE Trans. Electron Devices, Vol. 17, no.8, 1996.
[1.27] H. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous leakage current in LPCVD polysilicon MOSFET’s,” IEEE Trans. Electron Devices, vol. 32, pp. 1878-1884, 1985.
[1.28] K. R. Olasupo, and M. K. Hatalis, “Leakage current mechanism in sub-microm polysilicon thin-film transistors”, IEEE Trans. Electron Devices, vol. 43, pp. 1218-1223, 1996.
[1.29] K. Tanaka, H. Arai, and S. Kohda, “Characterization of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, pp. 23-25, 1988.
[1.30] B. H. Min, C. M. Park, and M. K. Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device Lett., vol. 16, pp. 161-163, 1995.
[1.31] C. M. Park, B. H. Min, J. H. Jun, J. S. Yoo, and M. K. Han, “Self-aligned offset gated Poly-Si TFT’s with a floating sub-gate,” IEEE Electron Device Lett., vol. 18, pp. 16-18, 1997.
[1.32] K. M. Chang, Y. H. Chung, G. M. Lin, J. H. Lin, and C. G. Deng, “A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions,” IEEE Electron Device Lett., vol. 22, pp. 472-474, 2001.
[1.33] C. T. Liu, and K. H. Lee, “An experimental study on the short-channel effects in undergated polysilicon thin film transistors with and without lightly doped drain structures,” IEEE Electron Device Lett., vol. 14, pp. 149-151, 1993.
[1.34] H. C. Lin, C. M. Yu, C. Y. Lin, K. L. Yeh, T. Y. Huang, and T. F. Lei, “A novel thin-film transistor with self-aligned field induced drain,” IEEE Electron Device Lett., vol. 22, No. 1, pp. 26-28, 2001.
[1.35] K. R. Olasupo, W. Yarbrough, and M. K. Hatalis, “The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, pp. 1306-1308, 1996.
[1.36] Lifshitz, S. Luryi, M. R. Pinto, and C. S. Rafferty, “Active-gate thin-film transistor,” IEEE Electron Device Lett., vol. 14, No. 8, pp. 394-396, 1993.
[2-1] Min-Koo Han et al., ”A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealing”, IEDM 2000.
[3.1] J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banarjee, “Anomalous leakage current in LPCVD polysilicon MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1878—1884, Sept. 1985.