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研究生:吳冠龍
研究生(外文):Wu Kuan Long
論文名稱:高鍺矽鍺之矽鎳化合物
論文名稱(外文):Formation of Ni Germano-Silicide on Single Crystalline Si0.3Ge0.7/Si
指導教授:荊鳳德
指導教授(外文):Albert Chin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:30
中文關鍵詞:
外文關鍵詞:germanium
相關次數:
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我們做了在矽鍺/矽(Si0.3Ge0.7/Si)基板上的金屬矽鍺化合物的研究,在此論文中作為金屬矽鍺化合物的金屬為鎳(Ni)與鈷(Co)。我們發現鎳金屬矽鍺化合物(Ni germano silicide)的片電阻可以在P+/N及N+/P的接面達到4-6歐姆/正方(4-6/)。 這個值遠比鈷金屬矽鍺化合物(Co germano silicide)小, 除此之外, 鎳金屬矽鍺化合物(Ni germano silicide) 在P+/N及N+/P接面的漏電流亦可以分別達到310-8 安培/公分平方與210-7 安培/公分平方( 310-8 A/cm2 and 210-7 A/cm2)如此低的電流密度。如此好的特性是歸因於相當平整的鎳金屬矽鍺化合物。

We have studied the Ni and Co germano-silicide on Si0.3Ge0.7/Si. The Ni germano-silicide shows a low sheet resistance of 4-6 / on both P+N and N+P junctions, which is much smaller than Co germano-silicide. Besides, small junction leakage currents of 310-8 A/cm2 and 210-7 A/cm2 are obtained for Ni germano-silicide on P+N and N+P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.

Table of Contents
Chinese Abstract…………………..…………………………..Ⅰ
English Abstract………………………………………………Ⅱ
Acknowledgement……………...……………………………. Ⅲ
Table of Contents…………………………………………….. Ⅳ
Chapter 1 Introduction……………………….……………….1
Chapter 2 Experiment………………………………………...3
Chapter 3 Results & Discussion……………………………...5
Chapter 4 Conclusion……………………….………………..7
Chapter 5 Reference………………………………………….8
Figure Captions………………………………………………11
Process Flow…………………………………………………12

[1]Y. H. Wu and A. Chin, “High temperature formed SiGe p-MOSFETs with good device characteristics,” IEEE Electron Device Lett. vol. 21, no. 7, pp. 350-352, 2000.
[2] Y. H. Wu, A. Chin, and W. J. Chen, “Thickness dependent gate oxide quality of thin thermal oxide grown on high temperature formed SiGe,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 289-292, 2000.
[3] Y.H. Wu, and A. Chin, “ Gate oxide integrity of thermal oxide grown on high temperature formed Si0.3Ge0.7,” IEEE Electron Device Lett., vol. 21, no. 3, pp.113-115. 2000.
[4] S. J. Lee, H. F. Luan, C. H. Lee, T. S. Jeon, W. P. Bai, Y. Senzaki, D. Roberts, D. L. Kwong, “Performance and reliability of ultra thin CVD HfO2 gate dielectrics with dual poly-Si gate electrodes,” in Symp. on VLSI Technology, 2001, pp. 133-134.
[5] X. Guo, X. Wang, Z. Luo, T. P. Ma, T. Tamagawa, “High quality ultra-thin (1.5 nm) TiO2-Si3N4 gate dielectric for deep sub-micron CMOS technology,” in IEDM Tech. Dig., 1999, pp. 137-140.
[6] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high-K Al2O3 gate dielectric with good mobility and low Dit,” in Symp. on VLSI Tech., 1999, pp. 135-136.
[7] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, “High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5-10Å,” in Symp. on VLSI Tech., 2000, pp. 16-17.
[8] J. H. Ku, C. J. Choi, S. Song, S. Choi, H. Fujuhara, H. K. Kang, and S. I. Lee, “High performance pMOSFETs with Ni(SixGei-x)/Poly-Si0.8Ge0.2 gate,” in Dig. Symp. VLSI Tech., 2000, pp. 114-115.
[9] C. P. Chao, K. E. Violette, S. Unnikrishnan, M. Nandakumar, R. L. Wise, J. A. Kittl, Q.Z. Hong, and I.C Chen,” Low resistance Ti or Co salicided raised source/drain transistors for sub 0.13m CMOS technology,” in IEDM Tech. Dig., 1997, pp. 103-106.
[10] Q. Z. Hong, W. T. Shiau, H. Yang, J. A. Kittl, C. P. Chao, H. L. Tsai, S. Krishnan, I. C. Chen, and R. H. Havemann, “CoSi2 with low diode leakage and low sheet resistance at 0.065m gate length,” in IEDM Tech. Dig., 1997, pp. 107-110.
[11] Q. Xiang, C. Woo, E. Paton, J. Foster, B. Yu and M. R. Lin,” Deep sub-100nm CMOS with ultra low gate sheet resistance by NiSi,” in Dig. Symp. VLSI Tech., 2000, pp. 76-77.

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