(54.236.58.220) 您好!臺灣時間:2021/03/05 05:57
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:李鐏鐶
研究生(外文):Tzuen-Hwan Lee
論文名稱:降低表面電場之側向擴散型金氧半電晶體之研究
論文名稱(外文):Study on Reduced-Surface-Field Lateral-Diffusion MOSFETs
指導教授:鄭晃忠鄭晃忠引用關係
指導教授(外文):Huang-Chung Cheng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:84
中文關鍵詞:降低表面電場側向擴散型金氧半電晶體側向雙擴散型金氧半電晶體重疊介面多重降低表面電場三元降低表面電場
外文關鍵詞:RESURFLDMOSsuper-junctionmulti-resurf3D RESURF
相關次數:
  • 被引用被引用:0
  • 點閱點閱:768
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:161
  • 收藏至我的研究室書目清單書目收藏:0
  本次研究探索了兩種高耐壓並且能和雙極性電晶體或金氧半電晶體整合在一起的功率元件:降低表面電場之側向擴散型金氧半電晶體和三元降低表面電場之側向擴散型金氧半電晶體。
  降低表面電場之側向擴散型金氧半電晶體主要的優點有二,第一,它具有高度的整合能力;第二,它在提供高耐壓的同時也能擁有一個很低的導通阻抗。製作這種元件的主要關鍵是精確的控制耐壓區內的摻雜量,在不影響導通阻抗的情況下,大量提昇其崩潰電壓。在本篇論文內,我們對這種元件有一詳細的研究與探討。
  近年來,一種新的耐壓結構被發明並製作出來,這種結構稱為重疊介面結構或是多重降低表面電場結構。它的主要特色是其摻雜溶度不會受其耐壓的影響,因此,在提供高耐壓的同時,這種結構尚保有一個很高的摻雜溶度,所以它的導通阻抗比起一般功率元件低很多。雖然這種結構已成功的嵌入於垂直式雙擴散金氧半電晶體以及絕緣層矽晶片上的降低表面電場之側向擴散型金氧半電晶體內,但是,少有研究是探索這種結構在一般矽晶片上的功效的。本次研究首次探索三元降低表面電場之側向擴散型金氧半電晶體在矽晶片上的性能。雖然因為製程設計上的不當與製程本身的限制,元件特性並未如預期中的好,但是這種元件一些特有的性質依然在本篇論文內完全呈現出來。

Two topics of the reduced-surface-field (RESURF) lateral-diffusion MOSFETs (LDMOS) and the three-dimensional (3D) RESURF LDMOS are studied in the thesis. These devices can be easily integrated with bipolar or MOS transistors due to their planar structures. Moreover, the process is compatible with the CMOS or the BiCMOS process.
The prime merits of the RESURF LDMOS are the high integration ability and the high breakdown voltage (BV) with a low on-resistance (Ron). The key for the device is to control the dose of the drift region precisely. When the RESURF action takes place, the BV is increased greatly with little degradation of the Ron.
In recent years, an innovative structure, called the super-junction or the multi-resurf structure, was invented. The out-standing feature of the structure is that the structure maintain a high doping concentration at high-voltage ratings, and hence a very small Ron. Although the structure has been implemented into the vertical double-diffusion MOSFETs (VDMOS) and onto the silicon-on-insulator (SOI) wafer, few researches were focused on that on the bulk-Si wafer. We first investigate the 3D RESURF LDMOS on the bulk-Si wafer in the study. Though the performance is not as good as expected because of the improper process design and the constraints of the process in the laboratory, some special features of the device are still presented in the thesis.

Chapter 1 Introduction
1.1 Overview of RESURF LDMOS
1.2 Overview of 3D RESURF LDMOS
1.3 Motivation
1.4 Thesis Outline
Chapter 2 RESURF LDMOS
2.1 Introduction
2.2 Mechanism of RESURF Principle
2.3 Simulation of RESURF LDMOS
2.3-1 Breakdown Voltage and Specific On-resistance
2.3-2 Safe-operation Area
2.4 Experimental Results of RESURF LDMOS
2.4-1 The Experimental Performance
2.4-2 Comparison between Experimental and Simulated Results
2-5 Summary
Chapter 3 3D RESURF LDMOS
3.1 Introduction
3.2 Overview of The Super-junction Structure and 3D RESURF LDMOS
3.2-1 The Super-junction Structure and COOLMOS
3.2-2 3D RESURF LDMOS
3.3 The Evaluation and Simulation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.3-1 The Evaluation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.3-2 Simulation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.4 Experimental Results of 3D RESURF LDMOS on The Bulk-Si Wafer
3.4-1 Experimental Results
3.4-2 Comparison between 3D RESURF LDMOS and RESURF LDMOS
3.5 Summary
Chapter 4 Conclusion
References
Chapter 1
Chapter 2
Chapter 3

[1-1] Coe, US-patent, 4,754,310, 1988.
[1-2] Chen, US-patent, 5,216,275, 1993.
[1-3] Tihanyi, US-patent, 5,438,215, 1995.
[1-4] COOLMOS is a trademark of Infineon Corporation.
[1-5] COOLMOS, the second generation, Infineon Corporation.
[1-6] F. Udrea, A. Popescu and W. Milne, “A new class of lateral power devices for HVIC's based on the 3D RESURF concept,” Bipolar/BiCMOS Circuits and Technology Meeting, pp.187-190, 1998.
[1-7] F. Udrea et al, “Ultra-high voltage device termination using the 3D RESURF (Super-junction) concept - experimental demonstration at 6.5 kV,” ISPSD’2001, pp.129-132, 2001.
[1-8] Tsuprem4 Version 98.4, Avant Corporation.
[1-9] Medici Version 4.1, Avant Corporation.
[1-10] Davnci Version 2000.4, Avant Corporation.
[1-11] SIMPOS is a trademark of Infineon Corporation.
[2-1] Satyen Mukherjee, “Power Integrated Circuits-Progress, Prospects and Challenges,” IEEE Trans. Electron Devices, vol. 36, no.11, pp.2599-2600, 1989.
[2-2] Adriaan W. Ludikhuize, “A Review of RESURF Technology,” ISPSD’2000, pp.11-18, 2000.
[2-3] Adriaan W. Ludikhuize, “A Versatile 700-1200V IC Process for Analog and Switch Applications,” IEEE Trans. Electron Devices, vol. 38, no. 7, pp.1582-1589, 1991.
[2-4] Adriaan W. Ludikhuize, “Self-aligned and Shielded-Resurf LDMOS for dense 20V Power IC’s,” ISPSD’1999, pp.81-84, 1999.
[2-5] R. Zhu et al, “A 65V, 0.56mΩ.cm2 Resurf LDMOS in a 0.35um CMOS Process,” ISPSD’2000, pp.335-338, 2000.
[2-6] Zahir Parpia, C. Andre T. Salama and Robert A. Hadaway, “A CMOS-Compatible High-Voltage IC Process,” IEEE Trans. Electron Devices, vol.35, no.10, pp.1687-1694, 1988.
[2-7] Jacob A. van der Pol et al, “A-BCD: An Economic 100V RESURF Silicon-On-Insulator BCD Technology for Consumer and Automotive Applications,” ISPSD’2000, pp.327-330, 2000.
[2-8] T. Latavic, J. Petruzzello, M. Simpson, J. Curcio and S. Mukherjee, “Lateral Smart-Discrete Process and Devices based on Thin-Layer Silicon-on-Insulator,” ISPSD’2001, pp.407-410, 2001.
[2-9] B. Jayant Baliga, “Power Semiconductor Devices,” PWS Publishing Company, 1996.
[2-10] Zahir Parpia and C. Andre T. Salama, “Optimization of RESURF LDMOS transistors: an analytical approach,” IEEE Trans. Electron Devices, vol.37, no.3, pp.789-796, 1990.
[2-11] S. Hidalgo, J. Fernandez, P. Godignon, J. Rebollo and J. Millan, “Power lateral DMOS transistor test structures,” Conference on Microelectronic Test Structure, vol.6, pp.33-38, 1993.
[2-12] Jin He and Xing Zhang, “Quasi-2-D analytical model for the surface field distribution and optimization of RESURF LDMOS transistor,” Microelectronics Journal, pp.655-663, 2001.
[2-13] S.M. Sze, “Physics of Semiconductor Devices 2nd Edition,” John Wiley & Sons, Inc., 1985.
[2-14] Y.S. Huang and B.J. Baliga, “Extension of RESURF principle to dielectrically isolated power devices,” ISPSD’1991, pp.27-30, 1991.
[2-15] S. Merchant et al, “Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors,” ISPSD’1993, pp.124-128, 1993.
[2-16] Wenhong Li and Jinsheng Luo, “A novel analytical physical model for thin film SOI RESURF structure based on 2-D Poisson equation,” Solid-State and Integrated Circuit Technology, pp.724-727, 1998.
[2-17] Sang-Koo Chung, “An Analytical Model for Breakdown Voltage of Surface Implanted SOI RESURF LDMOS,” IEEE Trans. Electron Devices, vol.47, no.5, pp.1006-1009, 2000.
[2-18] P. Hower, J. Lin, S. Merchant and S. Paiva, “Using Adaptive resurf to improve the SOA of LDMOS transistors,” ISPSD’2000, pp.345-348, 2000.
[2-19] Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu and Amitava Bose, “SOA improvement by a double RESURF LDMOS technique in a power IC technology,” IEDM Technical Digest, pp.75-78, 2000.
[2-20] Yuji Suzuki et al, “3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS,” SOI Conference, pp.134-135, 1996.
[3-1] G. Deboy, M. Marz, J.-P. Stengl, H. Strack, J. Tihanyi and H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of silicon,” IEDM Tech. Digest, pp.683-685, 1998.
[3-2] L. Lorenz, G. Deboy, A. Knapp and M. Marz, “COOLMOSTM — a new milestone in high voltage Power MOS,” ISPSD’1999, pp.3-10, 1999.
[3-3] COOLMOS, the second generation, Infineon Corporation.
[3-4] Praveen M. Shenoy, Anup Bhalla and Gary M. Dolny, “Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET,” ISPSD’1999, pp.99-102, 1999.
[3-5] T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada and S. Hine, “Which is cooler, trench or multi-epitaxy? Cutting edge approach for the silicon limit by the super trench power MOS-FET (STM),” ISPSD’2000, pp.73-76, 2000.
[3-6] Jack Glenn and Jim Siekkinen, “A Novel Vertical Deep Trench RESURF DMOS (VRT-DMOS),” ISPSD’2000, pp.197-200, 2000.
[3-7] R. Ng, F. Udrea, G. Amaratunga, “An analytical model for the 3D-RESURF effect,” Solid-State Electronics, pp.1753-1764, 2000.
[3-8] F. Udrea, A. Popescu and W. Milne, “The 3D RESURF junction,” Semiconductor Conference, CAS '98 Proceedings, pp.141-144, 1998.
[3-9] F. Udrea, A. Popescu and W. Milne, “A new class of lateral power devices for HVIC's based on the 3D RESURF concept,” Bipolar/BiCMOS Circuits and Technology Meeting, pp.187-190, 1998.
[3-10] R. Ng, F. Udrea, K. Sheng, K.Ueno, G.A.J. Amaratunga and M. Nishiura, “Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI,” ISPSD’2001, pp.395-398, 2001.
[3-11] Antonio G. M., Strollo and Ettore Napoli, “Optimal on-resistance versus breakdown voltage tradeoff in super-junction power devices: a novel analytical model,” IEEE Trans. Electron Devices, vol.48, no.9, pp.2161-2167, 2001.
[3-12] Rene P. Zingg, “New benchmark for RESURF, SOI and super-junction power devices,” ISPSD’20001, pp.343-346, 2001.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔