本論文研究的方向，主要著重於探討Negative-Bias-Temperature Instability (NBTI)對P型通道超薄閘極氧化層元件特性影響之研究。閘極介電層厚度隨著每個新的CMOS技術世代演進而持續縮減，主要的目的是為了減少短通道效應(short channel effects)的影響，並獲得較高的電流驅動能力(driving capability)。當閘極氧化層厚度變薄，對於閘極氧化層可靠度的需求也越來越高。近年來的一項重要發現指出，元件的使用期限(device lifetime)，可能取決於P型通道元件的NBTI特性，因此超薄氧化層的NBTI問題也就成為當今積體電路技術發展中最重要的課題。
首先，本論文介紹目前NBTI方面的相關研究，包括：NBTI發生的機制(diffusion control model)、臨界電壓(Vth)的飄動與閘極偏壓及溫度之間的相關性、以及閘極氧化層中的雜質對元件NBTI特性的影響。為了詳細了解NBTI現象的發生，我們製造了一批閘極氧化層厚度約為3 奈米的元件，並針對不同的閘極參雜(gate doping specious)，不同的氟原子含量，以及在疊完金屬之後的退火(Post Metal Annealing)處理的影響，做一個詳細探討與研究。
其次，我們針對閘極氧化層厚度為1.6奈米的元件，研究相關的NBTI效應。其中包含了兩種閘及氧化層材料：氧化矽以及氧化矽/氮化矽的疊層結構(N/O stack)。研究中發現，在氧化矽/氮化矽的疊層結構中，電洞很容易被捕捉住，造成以氧化矽/氮化矽為介電層材料的元件在高溫閘極負偏壓的條件下，有較大的臨界電壓飄動(Vth shift)。不過這些累積在介電層中的電洞，會穿透過底層的超薄氧化矽而回歸矽晶版，所以經過一段時間後，元件的特性可以稍稍的回覆。另外，我們將N型通道電晶體在高溫的環境下，做閘極正偏壓以及閘極負偏壓的研究，並和P型通道電晶體在高溫閘極負偏壓下的特性做一比較。實驗結果發現，電子穿隧電流(electron tunneling current) 並不會對閘極介電層造成太大的傷害，電洞穿隧電流(hole tunneling current)則具有較大的破壞力。

The reliability of ultra-thin gate oxide is one of the major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. In this thesis, the reliability issues regarding negative bias temperature instability (NBTI) of PMOSFETs having ultra-thin gate oxide for present and future ULSI technologies were extensively investigated and discussed. First, we started with a review of the present understanding of NBTI on PMOSFETs, the diffusion control model, the dependence of Vth shift on stress time and voltage, and the effects of impurities in oxide. To further understand the effects of NBTI on PMOSFETs, devices with 30Å gate oxide were made. Issues relating to the effects of gate doping species, device characteristics affected by F incorporation, and the effects of post metal annealing (PMA) were demonstrated.
Second, NBTI effects on devices with 16Å gate oxide and N/O stack were studied and compared. The different hole trapping mechanisms in oxide and N/O stack were discussed. Our experimental data shows that the extrapolated device lifetime from large Vg regime severely underestimate the realistic lifetime at low Vg regime. NBTI and positive bias temperature instability (PBTI) of NMOSFETs were compared to the NBTI of PMOSFETs to understand the role of electron tunneling current in NBTI. Our results show clearly that the electron tunneling current plays only an insignificant role in BT stress.
In conclusion, NBTI is very much process dependent, difference in gate dielectrics as well as impurities in dielectrics result in dramatic difference in the NBTI characteristics. In general, stronger interface strength usually results in better NBTI immunity (for devices with the same gate dielectric thickness). Thus, to improve the NBTI immunity, processes that degrade the interface quality should be avoided, if at all possible, such as plasma charging damage and boron penetration. On the other hand, processes that improve the interface should be employed, such as proper quantity of F incorporation, and PMA using deuterium.

Abstract(Chinese) I
Abstract(English) III
Acknowledgment V
Contents VI
Table Captions VII
Figure Captions VIII
Chapter1 Introduction 1
1.1. Background 1
1.2. Researches about NBTI 2
1.3. Diffusion-Limited Reaction Model 3
1.4 Organization of This Thesis 5
Chapter2 NBTI of PMOSFETs with 3 nm-thick Gate Oxide 6
2.1 Device Fabrication and Characterization 6
2.2 Results and Discussion 7
2.2.1 Effects of poly-Si gate doping type 7
2.2.2 NBTI of B+- and BF2+-implanted samples 8
2.2.3 Effects of post-metal-annealing 9
2.3 Summary 10
Chapter 3 NBTI in PMOSFETs with Ultra-Thin (1.6 nm) Oxide or Nitride/Oxide Stack Gate Dielectric 12
3.1 Device Fabrication and Characterization 12
3.2 The Effects of Hole and Electron Current on NBTI 13
3.3 NBIT Difference between Oxide and N/O Stack 14
3.4 Summary 15
Chapter 4 Conclusions and Future Work 17
4.1 Conclusions 17
4.2 Future Work 18
Reference: 19

Reference:
[1] J. R. Ligenza and W. G. Spitzer, “The mechanisms for silicon oxidation in steam and oxygen”, J. Phys. Chem. Solids 14, 131 1960.
[2] D. A. Buchanan, ”Scaling the gate dielectric: material integration, and reliability”, IBM J. Res. Develop. Vol. 43 No. 3, May 1999
[3] Iwai H, “The future of ultra-small geometry MOSFETS beyond 0.1 micron”, Microelectronic Engineering 1995,28(1-4):147-54
[4] Toyoshima Y. “Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET''s”, IEEE Trans. Electron Devices, Vol. 37 No. 6 June 1990
[5] Paul Heremans, “ Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs ”IEEE Trans. Electron Devices,Vol. 35 No. 12 Dec. 1988
[6] Hisayo Sasaki Momose, “1.5nm Direct-Tunneling Gate Oxide Si MOSFET’s”, IEEE Trans. Electron Devices, Vol. 43, No. 8, Aug. 1996
[7] N. Kimizuka, T. Yamamoto, T. Mogami, et al., “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling” Symp. VLSI Tech. 1999, p.73.
[8] E. H. Nicolian and J. T. Brews, MOS Phsics and Technology (Wiley-Interscience, New York, 1982), pp. 794-798.
[9] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. Soc. 114, 267 (1967).
[10] A. Goetzberger, A. D. Lopez. And R. J. Strain, J. Electrochem Soc. 120, 90 (1973).
[11] N. Shiono, 0. Nakajima, and C. Hashimoto, J. Electrochem. Soc. 130, 138 (1983).
[12] K. 0. Jeppson and C. M. Svensson, J. Appl. Phys. 48, 2004 (1977).
[13] K. Uwasawa, T. Mogami, T. Kunio, and M. Fukuma, “Scaling lim-itations of gate oxide in p + polysilicon gate MOS structures for sub-quarter-micron CMOS devices,” in IEDM Tech Dig., 1993, p. 895.
[14] J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrilo, “The effects of boron penetration on p+- polysilicon gated PMOS devices,” IEEE Trans. Electron Devices, Vol. 37, p.1842, Aug. 1990.
[15] N. Kimizuka, K. Yamaguchi, K. Imai, et al., “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation” Symp. VLSI Tech. 2000, p. 92
[16] C. E. Blat, “Mechanism of negative bias temperature instability” J. Appl. Phsys. 69(3), 1 February 1991
[17] E. da Silva, Y. Nishioka, and T. Ma, “Dramatic improvement of hot-carrier-induced interface degradation in MOS structures containing F or Cl in SiO2”, IEEE Electron Device Lett., Vol. 9, pp. 38—40,Jan. 1988.
[18] Shigeo Ogawa, Masakazu Shimaya, and Noboru Shiono, ”Interface trape generation at ultrathin SiO2 (4-6 nm) interfaces during negative-bias temperature aging”, J. Appl. Phys. 77(3), February 1995
[19] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon”, J. Mater. Res., Vol. 11 No. 11, Nov. 1996
[20] G. Timp, A. Agarwal, F. H. Baumann, “Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs”, IEDM Tech. Dig., p.930, 1997
[21] G. D. Wilk, ”Silicate Gate Dielectrics for Scaled CMOS”
[22] C Svensson, “The Physics of SiO2 and its Interface”, edited by S. T. Pantelides (Pergamon, New York, 1978) p. 328.
[23] K. O. Jeppson and C. M. Svensson, J. Appl. Phys. 48, 2004 (1977).
[24] N. Shiono and T. Yashiro, Jpn. J. Appl. Phys. 18, 1087 (1979).
[25] C. H. Liu, M. T. Lee, C. Y. Lin, et al., “Mechanism and Process Dependence of Negative Bias Temperature Instability (NBTI) for PMOSFETS with Ultrathin Gate Dielectrics”, IEEE/IEDM 2001, p.861.
[26] Y. Shi, T. P. Ma, S. Prasad, et al.,”Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET’s”, IEEE/ED, Vol. 45, No. 11, Nov. 1998, p.2355.
[27] H. J. Whitlow et al., “Fluorine in low-pressure chemical vapor deposited W/Si contact structures: Inclusion and thermal stability.”, Appl. Phys. Lett., Vol. 50, p.1497, May 1987.
[28] M. Delfino, M.E. Lunnon, “A structural and electrical comparison of BCl and BF2 ion implanted silicon.”, J. Electrochem. Soc., Vol. 132, p.435, Feb. 1985.
[29] D. K. Sadana, W. Maszara, J. J. Wortmann et al., “Germanium implantation into Silicon”, J. Electrochem. Soc., Vol. 131, p.943, Apr. 1984
[30] P. Chowdhury et al., “Improvement of ultrathin gate oxide and oxyni-tride integrity using fluorine implantation technique,” Appl. Phys. Lett., Vol. 70, No. 1, pp. 37—39, 1997.
[31] G. Innertsberger et al., “The influence of fluorine on various MOS devices,” in Proc. Symp. Ultrathin SiO and High-K Materials for ULSI Gate Dielectrics, San Francisco, CA, 1999, pp. 589—595.
[32] T. B. Hook, E. Adler, F. Guarin, “The Effect of Fluorine on Parametrics and Teliability in a 0.18mm 3.5/6.8 nm Dual Gate Oxide CMOS”, IEEE/ED, Vol. 48, No. 7, p.1346, July 2001
[33] M. Cao et al., “Boron diffusion and penetration in ultrathin oxide with Poly-Si gate,” IEEE Electron Device Lett., Vol. 19, pp. 291—293, Aug. 1998.
[34] J.Y. Tsai et al., “Slight gate oxide thickness increase in PMOS devices with BF implanted polysilicon gate,” IEEE Electron Device Lett., Vol.19, pp. 348—350, Feb. 1998.
[35] P. Wright and K. Saraswat, “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Trans. Electron Devices, Vol. 36, pp. 879—889, May 1989.
[36] T. Yamamoto, K Uwasawa, T Mogami, “Bias Temperature Instability in Scaled P+ Polysilicon Gate p-MOOSFET’s”, IEEE/ED, Vol. 46, No. 5, 1999, p.921.
[37] G. D. Wilk, B. Brar,” Electrical characteristics of high-quality sub-25-/spl Aring/ oxides grown by ultraviolet ozone exposure at low temperature”, IEEE Electron Device Letters, Vol. 20 No. 3, March 1999 ,p.132
[38] C. G. Parker, G. Lucovsky, and J. R. Hauser, “Ultrathin oxide—nitride gate dielectric MOSFETs,” IEEE Electron Device Lett., Vol. 19, NO. 4, pp.106—108, 1998.
[39] S. F. Ting, Y. K. Fang, C. W. Yang et al., “The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 mm CMOS technology and beyond”, IEEE Electron Device Lett., Vol. 22, No. 7, p.327, July 2001.