|
Reference: [1] J. R. Ligenza and W. G. Spitzer, “The mechanisms for silicon oxidation in steam and oxygen”, J. Phys. Chem. Solids 14, 131 1960. [2] D. A. Buchanan, ”Scaling the gate dielectric: material integration, and reliability”, IBM J. Res. Develop. Vol. 43 No. 3, May 1999 [3] Iwai H, “The future of ultra-small geometry MOSFETS beyond 0.1 micron”, Microelectronic Engineering 1995,28(1-4):147-54 [4] Toyoshima Y. “Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET''s”, IEEE Trans. Electron Devices, Vol. 37 No. 6 June 1990 [5] Paul Heremans, “ Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs ”IEEE Trans. Electron Devices,Vol. 35 No. 12 Dec. 1988 [6] Hisayo Sasaki Momose, “1.5nm Direct-Tunneling Gate Oxide Si MOSFET’s”, IEEE Trans. Electron Devices, Vol. 43, No. 8, Aug. 1996 [7] N. Kimizuka, T. Yamamoto, T. Mogami, et al., “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling” Symp. VLSI Tech. 1999, p.73. [8] E. H. Nicolian and J. T. Brews, MOS Phsics and Technology (Wiley-Interscience, New York, 1982), pp. 794-798. [9] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. Soc. 114, 267 (1967). [10] A. Goetzberger, A. D. Lopez. And R. J. Strain, J. Electrochem Soc. 120, 90 (1973). [11] N. Shiono, 0. Nakajima, and C. Hashimoto, J. Electrochem. Soc. 130, 138 (1983). [12] K. 0. Jeppson and C. M. Svensson, J. Appl. Phys. 48, 2004 (1977). [13] K. Uwasawa, T. Mogami, T. Kunio, and M. Fukuma, “Scaling lim-itations of gate oxide in p + polysilicon gate MOS structures for sub-quarter-micron CMOS devices,” in IEDM Tech Dig., 1993, p. 895. [14] J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. W. Miller, C. D. Gunderson, and L. C. Parrilo, “The effects of boron penetration on p+- polysilicon gated PMOS devices,” IEEE Trans. Electron Devices, Vol. 37, p.1842, Aug. 1990. [15] N. Kimizuka, K. Yamaguchi, K. Imai, et al., “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation” Symp. VLSI Tech. 2000, p. 92 [16] C. E. Blat, “Mechanism of negative bias temperature instability” J. Appl. Phsys. 69(3), 1 February 1991 [17] E. da Silva, Y. Nishioka, and T. Ma, “Dramatic improvement of hot-carrier-induced interface degradation in MOS structures containing F or Cl in SiO2”, IEEE Electron Device Lett., Vol. 9, pp. 38—40,Jan. 1988. [18] Shigeo Ogawa, Masakazu Shimaya, and Noboru Shiono, ”Interface trape generation at ultrathin SiO2 (4-6 nm) interfaces during negative-bias temperature aging”, J. Appl. Phys. 77(3), February 1995 [19] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon”, J. Mater. Res., Vol. 11 No. 11, Nov. 1996 [20] G. Timp, A. Agarwal, F. H. Baumann, “Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs”, IEDM Tech. Dig., p.930, 1997 [21] G. D. Wilk, ”Silicate Gate Dielectrics for Scaled CMOS” [22] C Svensson, “The Physics of SiO2 and its Interface”, edited by S. T. Pantelides (Pergamon, New York, 1978) p. 328. [23] K. O. Jeppson and C. M. Svensson, J. Appl. Phys. 48, 2004 (1977). [24] N. Shiono and T. Yashiro, Jpn. J. Appl. Phys. 18, 1087 (1979). [25] C. H. Liu, M. T. Lee, C. Y. Lin, et al., “Mechanism and Process Dependence of Negative Bias Temperature Instability (NBTI) for PMOSFETS with Ultrathin Gate Dielectrics”, IEEE/IEDM 2001, p.861. [26] Y. Shi, T. P. Ma, S. Prasad, et al.,”Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET’s”, IEEE/ED, Vol. 45, No. 11, Nov. 1998, p.2355. [27] H. J. Whitlow et al., “Fluorine in low-pressure chemical vapor deposited W/Si contact structures: Inclusion and thermal stability.”, Appl. Phys. Lett., Vol. 50, p.1497, May 1987. [28] M. Delfino, M.E. Lunnon, “A structural and electrical comparison of BCl and BF2 ion implanted silicon.”, J. Electrochem. Soc., Vol. 132, p.435, Feb. 1985. [29] D. K. Sadana, W. Maszara, J. J. Wortmann et al., “Germanium implantation into Silicon”, J. Electrochem. Soc., Vol. 131, p.943, Apr. 1984 [30] P. Chowdhury et al., “Improvement of ultrathin gate oxide and oxyni-tride integrity using fluorine implantation technique,” Appl. Phys. Lett., Vol. 70, No. 1, pp. 37—39, 1997. [31] G. Innertsberger et al., “The influence of fluorine on various MOS devices,” in Proc. Symp. Ultrathin SiO and High-K Materials for ULSI Gate Dielectrics, San Francisco, CA, 1999, pp. 589—595. [32] T. B. Hook, E. Adler, F. Guarin, “The Effect of Fluorine on Parametrics and Teliability in a 0.18mm 3.5/6.8 nm Dual Gate Oxide CMOS”, IEEE/ED, Vol. 48, No. 7, p.1346, July 2001 [33] M. Cao et al., “Boron diffusion and penetration in ultrathin oxide with Poly-Si gate,” IEEE Electron Device Lett., Vol. 19, pp. 291—293, Aug. 1998. [34] J.Y. Tsai et al., “Slight gate oxide thickness increase in PMOS devices with BF implanted polysilicon gate,” IEEE Electron Device Lett., Vol.19, pp. 348—350, Feb. 1998. [35] P. Wright and K. Saraswat, “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Trans. Electron Devices, Vol. 36, pp. 879—889, May 1989. [36] T. Yamamoto, K Uwasawa, T Mogami, “Bias Temperature Instability in Scaled P+ Polysilicon Gate p-MOOSFET’s”, IEEE/ED, Vol. 46, No. 5, 1999, p.921. [37] G. D. Wilk, B. Brar,” Electrical characteristics of high-quality sub-25-/spl Aring/ oxides grown by ultraviolet ozone exposure at low temperature”, IEEE Electron Device Letters, Vol. 20 No. 3, March 1999 ,p.132 [38] C. G. Parker, G. Lucovsky, and J. R. Hauser, “Ultrathin oxide—nitride gate dielectric MOSFETs,” IEEE Electron Device Lett., Vol. 19, NO. 4, pp.106—108, 1998. [39] S. F. Ting, Y. K. Fang, C. W. Yang et al., “The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 mm CMOS technology and beyond”, IEEE Electron Device Lett., Vol. 22, No. 7, p.327, July 2001.
|