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研究生:洪燕萍
研究生(外文):Yen-ping Hung
論文名稱:氨氣預處理及不同後續退火技術改善銫金屬氧化層之研究
論文名稱(外文):Cerium-based Gate Dielectrics with NH3 Pretreatment and Various Post Annealing Techniques
指導教授:雷添福
指導教授(外文):Tan-Fu Lei
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:92
中文關鍵詞:二氧化銫
外文關鍵詞:CeO2
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在將來的MOS世代演進中,利用高介電常數的材料取代現今二氧化矽介電層技術是必要的趨勢.不幸地,許多具備高介電常數的材料在直接疊在矽基質上時,會因熱不穩定性的問題,常常需要在製程上多加一層阻障層,而增加製程上的複雜度和介電層製薄技術的困難度.二氧化銫和矽基板具有較佳的晶格匹配性以及高介電常數(約26),因此二氧化銫在未來的閘極介電層上具有較大的發展潛力.
在本論文中,我們研究以往未曾研究過有關於銫金屬氧化物的物性,電性以及可靠度分析.利用電子槍蒸鍍系統在矽基板上鍍銫金屬氧化物,並在蒸鍍前利用不同的預處理方式(NH3低壓化學氣相沈積,Cl2和CHF3電漿前置處理),和不同的後續退火技術(高溫爐管,N2O電漿和N2氣體快速退火), 藉以分析此介電層之電性及物性之變化. 結果顯示經由NH3氣體低壓化學氣相沈積預處理,以及後續N2O電漿和N2氣體快速退火處理後,使得二氧化銫具有較佳的電性如低漏電流,大崩潰電場,良好的熱穩定性及可靠度.這些研究成果顯示,對於未來介電層和低溫多晶矽TFT的應用,二氧化銫可以提供一個不錯的選擇.

In the coming MOS generations, gate dielectric materials having high dielectric constant, are needed for future gate dielectric application. Unfortunately, many high-k materials are thermally unstable when directly contacted with silicon and need an additional barrier layer which may add process complexity and impose thickness scaling limit. CeO2 has a lattice mismatch to Si estimated to be 0.35%, and a high dielectric constant(~26). It has potential advantage for the gate dielectric application.
In this thesis, physical, electrical and reliability characteristics of ultra thin Ce-based oxide as an alternative gate dielectric were studied for the first time. We present a systematic study of Ce-based gate dielectrics by dual E-gun, with different pretreatment (LPCVD in NH3 ambient, Cl2 plasma and CHF3 plasma), and various post anneal conditions (Furnace, N2O plasma and RTAN2). Excellent dielectric properties of CeO2 such as low leakage current, high breakdown field, good thermal stability, and good reliability were demonstrated after the NH3 pretreatment and post treatment of N2O plasma and RTAN2. These results suggest that CeO2 is a promising material for the future gate dielectric and low temperature poly TFT application.

Contents
Abstract(Chinese)………………………………………………………………I
Abstract(English)………………………………………………………………II
Acknowledge………………………………………………………………………III
Contents……………………………………………………………………………IV
Table & Figure Captions………………………………………… ………………VII
Chapter 1 Introduction………………………………………………………….1
1.1 Background………………..………………………………………………...1
1.2 Motivation………….………………………………………………………..2
1.3 The Fundamentals of This Research…………………………………………3
1.4 Characterizations of CeO2……………………….…………………………..4
1.5 Organization of the Thesis……………………………………..……………5
1.6 References…………………………………………………………………...6
Chapter 2 Characterizations of CexOy Gate Dielectric (Target:Ce) with NH3 pretreatment and post Annealing techniques…………………….…10
2.1 Introduction………………………………………………………………….10
2.2 Experiment procedure……………………………………………………….11
2.3 Results and Discussion………………………………………………………12
2.3.1 Electrical Properties of CexOy Gate Dielectric.………………………..12
2.3.1.1 J-V Characteristics……………………………………………….12
2.3.1.2 C-V Characteristics………………………………………………14
2.3.1.3 Characteristics of Electric Breakdown…………………………...15
2.3.1.4 Characteristics of Gate-leakage current density………………….15
2.3.1.5 Time Dependent Dielectric Breakdown………………………….16
2.4 Summary……………………………………………………………………..17
2.5 References……………………………………………………………………18
Chapter 3 Characterizations of Zr/Ce Oxide Gate Dielectric with NH3 pretreatment and post Annealing techniques……………………..31
3.1 Introduction…………………………………………………………………..31
3.2 Experiment procedure………………………………………………………..32
3.3 Results and Discussion……………………………………………………….33
3.3.1 Electric characteristics of Zr/Ce Oxide Gate Dielectric………………..33
3.3.1.1 J-V Characteristics……………………………………………….33
3.3.1.2 C-V Characteristics…………………….…………………………34
3.3.1.3 Characteristics of Electric Breakdown……………………………35
3.3.1.4 Characteristics of Gate-leakage current density………………….35
3.3.1.5 Time Dependent Dielectric Breakdown………………………….35
3.4 Summary……………………………………………………………………...36
3.5 References…………………………………………………………………….37
Chapter 4 Characterizations of CeO2 Gate Dielectrics (Target: CeO2) with NH3 Pretreatment and Various Post Annealing Techniques.……..50
4.1 Introducion…………………………….……………………………………..50
4.2 Experiment procedure…………………………………………………………51
4.3 Results and Discussion……………………………………………………….52
4.3.1 Material Analyses………………………………………………………52
4.3.2 Effects of NH3 Pretreatment and Post Furnace Annealing……………..53
4.3.2.1 J-V Characteristics………………………………………………..53
4.3.2.2 C-V Characteristics……………………………………………….54
4.3.2.3 Characteristics of Electric Breakdown ………………………….55
4.3.2.4 Characteristics of Gate-leakage current density…………………55
4.3.2.5 Time Dependent Dielectric Breakdown………………………….56
4.3.2.6 Characteristics of Hysteresis Phenomenon………………………57
4.3.3 Effects of N2O Plasma Post-deposited treatment and RTAN2 Annealing
4.3.3.1 J-V Characteristics……………………………………………….58
4.3.3.2 C-V Characteristics………………………………………………59
4.3.3.3 Characteristics of Electric Breakdown……………………………59
4.3.3.4 Characteristics of Gate-leakage current density…………………..60
4.3.3.5 Time Dependent Dielectric Breakdown…………………………..60
4.3.3.6 Characteristics of Hysteresis Phenomenon……………………….60
4.3.4 Comparison between Surface Nitridation and Post Nitridation after The Treatment of Post Annealing…………………………………………61
4.3.4.1 Thermal Stability…………………………………………………61
4.3.4.2 Characteristics of Leakage Current Versus EOT Trends…………61
4.3.5 Summary………………………………………………………………..62
4.3.6 References………………………………………………………………63
Chapter 5 Conclusions…………………………….…………………………….91
Vita

1.6 References
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2.5 References
[1] B. H. Lee et al., “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si”, IDEM Tech. Dig., p. 133, 1999.
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[6] T. Inoue, Y. Yamamoto, S. Koyama, S. Suzuki, and Y. Ueda, “Epitaxial growth of CeO2 layers on silicon”, Appl. Phys. Lett. 56, 1332 (1990).
[7] T. Inoue, T. Oshuna, L. Luo, X. Wu, C. Maggiore, Y. Yamamoto, Y. Saku-rai, and J. Chang, “Growth of (110)-oriented CeO2 layers on (100) silicon substrates”, Appl. Phys. Lett. 59, 3604 (1991).
[8] H. Koinuma, H. Nagata, T. Tsukshara, S. Gonda, and M. Yoshimoto, Ex-tended Abstracts of the 22nd Conference on Solid State Devices and Ma-terials, Sendai, Japan, 1990 (unpublished), p. 933.
[9] L. Tye, Y. He, R. Leonard, N. El-Masry, and S. M. Bedair, presented at the 35th Electronic Materials Conference, Santa Barbara, CA, 1993 (unpub-lished).
[10] H. Koinuma, H. Nagata, T. Tsukshara, S. Gonda, and M. Yoshimoto, “Ceramic layer epitaxy by pulsed laser deposition in an ultrahigh vacuum system”, Appl. Phys. Lett. 58, 2027 (1991).
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3.5 References
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[4] Y. Ma, Y. Ono, L. Stecker, D. R. Evans, and S.T. Hsu, “Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process,” in IEDM Tech. Dig., 1999, pp. 136-139.
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[9] Z. J. Luo, T. P. Ma, E. Cartier, M. Copel, T. Tamagawa, and B. Halpern, “Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate applications,” in VLSI Tech. Symp. Dig., 2001, pp. 135-136.
[10] M. Balog, M. Schieber, M. Michman, and S. Patai, “The chamical vapor deposition and characterization of ZrO2 films from organometallic compounds,” Thin Solid Films, 47, pp.109, 1977.
[11] G. D. Wilk, and R. M. Wallace, “Stable zirconium silicate gate dielectrics deposited directly on silicon,” Applied. Physics. Letters, vol. 76, no. 1, pp. 112-114, 3 Jan. 2000.
[12] M. Copel, M. Gribelyuk, and E. Gusev, “Structure and stability of ultrathin zirconium oxide layers on Si(001),” Applied. Physics. Letters, vol. 76, no. 4, pp. 436-438, 24 Jan. 2000.
[13] T. Ngai, W. J. Qi, R. Sharma, J. Fretwell, X. Chen, J. C. Lee, and S. Banerjee, “Electrical properties of ZrO2 gate dielectric on SiGe,” Applied. Physics. Letters, vol. 76, no. 4, pp. 502-504, 24 Jan. 2000.
[14] C. M. Perkins, B. B. Triplett, P. C. Mclntyre, K. C. Saraswat, S. Haukka, and M. Tuomminen, “Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition,” Applied. Physics. Letters, vol. 78, no. 16, pp. 2357-2359, 16 April 2001.
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[16] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advanced gate dielectrics,” Journal of Applied Physics, vol. 87, no. 1, pp. 484-492, 1 Jan. 2000.
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[19] T Inoue, Y. Yamamoto, S. Koyama, and S. Suzuki, “Epitaxial growth of CeO2 layers on silicon”, Appl. Phys. Lett. 56, 1332(1990).
[20] T. Chikyowa, S. M. Bedair, L. Tye and N. A. El-Masry, Appl. Phys. Lett. Vol. 65, No. 8, 22 August 1994.
4.5 References
[1] B. H. Lee et al, “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8-12Å)”, IEDM Tech Dig., 2000, p. 39.
[2] C. H Lee et al, “MOS devices with high quality ultra thin CVD ZrO2 gate dielectrics and self aligned TaN and TaN/poly gate electrodes”, Symp VLSI Tech. Dig., 2001, p. 137.
[3] T. Inoue, Y. Yamamoto, S. Koyama, S. Suzuki, and Y. Ueda, “Epitaxial growth of CeO2 layers on silicon”, Appl. Phys. Lett. 56, 1332 (1990).
[4] T. Inoue, T. Oshuna, L. Luo, X. Wu, C. Maggiore, Y. Yamamoto, Y. Saku-rai, and J. Chang, “Growth of (110)-oriented CeO2 layers on (100) silicon substrates”, Appl. Phys. Lett. 59, 3604 (1991).
[5] H. Koinuma, H. Nagata, T. Tsukshara, S. Gonda, and M. Yoshimoto, Ex-tended Abstracts of the 22nd Conference on Solid State Devices and Ma-terials, Sendai, Japan, 1990 (unpublished), p. 933.
[6] L. Tye, Y. He, R. Leonard, N. El-Masry, and S. M. Bedair, presented at the 35th Electronic Materials Conference, Santa Barbara, CA, 1993 (unpub-lished).
[7] H. Koinuma, H. Nagata, T. Tsukshara, S. Gonda, and M. Yoshimoto, “Ceramic layer epitaxy by pulsed laser deposition in an ultrahigh vacuum system”, Appl. Phys. Lett. 58, 2027 (1991).
[8] H. Nagata, T. Tsukshara, S. Gonda, M. Yoshimoto, and H. Koinuma, Jpn. J. Appl. Phys. 30, L1136 (1991).
[9] T. Chikyow, L. Tye, N. A. El-Masry, and S. M. Bedair, Appl. Phys. Lett. 65, 1030 (1994).
[10] T. Chikyow, L. Tye, N. A. El-Masry, and S. M. Bedair, Mater. Res. Soc. Symp. Proc. 341 (in press).
[11] M. Yoshimoto, H. Nagata et al, Jpn. J. Appl. Phys. 29, L1199 (1990).

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