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研究生:黃建凱
研究生(外文):Chien-Kai Huang
論文名稱:低熔點基板上主動式元件關鍵製程開發
論文名稱(外文):Key Process Development of Active Devices on Low-melting Temperature Substrate
指導教授:葉清發
指導教授(外文):Ching-Fa Yeh
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:低熔點基板薄膜電晶體
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  • 被引用被引用:0
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利用複晶矽薄膜電晶體製作主動式陣列顯示器及周邊驅動電路於玻璃或塑膠等低熔點基板已是目前及未來平面顯示器的趨勢,然而受限於低熔點基板上的製程溫度,高品質的複晶矽薄膜電晶體製程相當困難。在本論文中,我們提出一種新的基板轉移技術利用背向蝕刻的方式,可將元件由矽基板上轉移到玻璃或是塑膠等低熔點基板上。
首先,用傳統的矽基板製程技術將高品質的複晶矽薄膜電晶體製作在矽基板上,接著將做好的複晶矽薄膜電晶體黏貼在玻璃或是塑膠等低熔點基板上。先用化學式機械研磨(CMP)再搭配濕式蝕刻溶液,或是完全使用濕式蝕刻溶液來將背面的矽基板蝕刻。使用完全濕式蝕刻溶液蝕刻是為了避免化學式機械研磨(CMP)時對可撓曲基板的傷害,並開發出最佳化的濕式蝕刻條件。我們由複晶矽薄膜電晶體的電特性可證明此背向蝕刻的基板轉移技術之可行性,其製程技術對元件幾乎不會產生傷害。此外,在論文中我們也討論了多種矽蝕刻溶液的特性。
利用此背向蝕刻的基板轉移技術可以突破在低熔點基板上製程溫度的限制。結合傳統CMOS的製程,我們可以在低熔點基板上做出極高品質的複晶矽薄膜電晶體。

The active matrix liquid-crystal display (AMLCD) and peripheral drivers combined with the high performance poly-Si TFTs on the glass/plastic or other low melting substrates is the trend now. Nevertheless, the process temperature limitation on the low-melting substrates is still a serious issue. In this thesis, a novel Devices Transfer Technology by Backside Etching (DTTBE) method that makes it possible to transfer thin-film devices from Si wafers to glass or plastic substrate has been investigated. This method breaks though the process temperature limitation on the low-melting substrates.
First, high performance poly-Si TFTs were fabricated on the Si wafer and then adhered to glass or plastic substrates. The remaining Si was removed delicately using wafer backside CMP and wet chemical etching or only entire chemical wet etching without CMP. Besides, in order to achieve the chemical silicon thinning process, for flexible substrates various silicon etchers were investigated in this thesis. In both methods of backside thinning the transferred devices exhibit no electrical degradation or yield loss in our research.
Therefore, for high-quality display application on low-melting temperature substrates, the novel transfer technique is quite attractive because of no process temperature limitation and its fully compatibility with conventional CMOS technology.

Contents
Chinese Abstract
English Abstract
Acknowledgment
Contents
Table Captions
Figure Captions
Chapter 1 introduction
1.1 General Background and Motivation
1.2 Organization of Thesis
Chapter 2 Poly-TFT manufactured on rigid substrate by DTTBE
2.1 Introduction
2.2 Experiment
2.2.1 Samples for DTTBE
2.2.1.1 TFT Fabrication
2.2.1.2 Bonding Process
2.2.2 First Step Thinning Process by CMP
2.2.3 Second Step Thinning Process by Wet Etching
2.2.4 Backside Electrode Patterned
2.3 Results and Discussion
2.3.1 Sample Preparation Related Issues
2.3.2 The Observation after Etching
2.3.3 Electrical Characteristics and Their Analyses
2.4 Summary
Chapter 3 Poly-TFT manufactured on flexible substrate by DTTBE
3.1 Introduction
3.2 Wet etching mechanism
Experiment
3.3.1 TFT and Resistor and Testing Structures
3.3.2 The Bonding Processes
3.3.3 Silicon-Etcher Solution
3.3.4 KOH Solution
3.3.5 The Backside Wet Etching Thinning Process
3.4 Results and Discussion
3.4.1 Sample Preparation related Issues
3.4.2 The Effect of Silicon Etcher
3.4.3 The Effect of KOH Etching
3.4.4 Samples Observation and Electrical Characteristics Analyses
3.5 Summary
Chapter 4 Conclusion
4.1 Conclusion
4.2 Future Works
References

Reference
Chapter 1
[1] Kinoshita H, et al. “High-resolution AMLCD made with a-Si:H TFTs and with an Al-gate and IZO last structure,” Society of Information Display Digest, pp.736- 741, 1999
[2] Koichi Kanzaki et al. “Direction of Low-Temperature p-Si Technology,” Society of Information Display Digest, pp. 242 — pp. 245, 2001
[3] Mark Stewart et al. “Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp.845, 2001
[4] I. W. Wu, et al. “Low temperature poly-Si TFT technology for AMLCD application,” AMLCD, pp. 7—10, 1995
[5] T. Serikawa, et al. “Low temperature fabrication of high mobility poly-Si TFT’s for large-area LCD’s,” IEEE Trans. Electron Devices, vol. 36, pp. 1929—1933, 1989
[6] J. Jang, et al. “Low temperature polycrystalline silicon thin film transistors” Elsevier Science Ltd vol. 51 no.4 pp. 769 — 775 1998
[7] I. W. Wu, et al. “Poly-Si TFT LCD technology and prospect of future displays,” EDMS, pp. 309—312 1997
[8] T. W. Little, et al. “Low temperature poly-Si TFTs using solid phase crystallization of very thin films and electron cyclotron resonance chemical vapor deposition gate insulator,” JJAP. vol. 30, no. 12B, pp. 3724—3728, 1991
[9] Xiangbin Zeng, et al. “A Novel Two-Step Laser Crystallization Technique for Low-Temperature Poly-Si TFTs” IEEE Transactions on Electron Devices, vol. 48, No. 5, MAY 2001
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[12] H. J. Kim et al. “New excimer-laser-crystallization method for producing large-grained and grain boundary-location-controlled Si films for thin film transistors,” Application Phys. Letter., vol. 68, p. 1513, 1996
[13] G. K. Giust, et al. “Low-temperature poly-silicon thin-film transistors fabricated from laser-processed puttered-silicon films,” IEEE Electron Device Letter, vol. 19, pp. 43—344, 1998
[14] Sigmon T, at el. “High-performance laser-processed polysilicon thin-film transistors” IEEE Electron Device Letters, vol. 20 Issue: 2, pp. 77- 78, Feb. 1999
[15] S. W. Lee et al. “Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization,” IEEE Electron Device Letters, vol. 17, pp. 160—162, Apr. 1996
[16] Y. Wang, et al. “Solid-phase crystallization and dopant activation of amorphous silicon films by pulsed rapid thermal annealing,” Appl. Surf. Sci., vol. 135, pp. 205—208, 1998
[17] Jin, H. K. Kwok et al. “Performance of thin-film transistors with ultrathin Ni-MILC polycrystalline silicon channel layers,” IEEE Electron Device Letters, vol. 20, pp. 167—169, 1999
[18] S. Jagar, et al. “Single grain thin-film-transistor (TFT) with SOI COMS performance formed by metal-induced-lateral-crystallization,” IEDM, pp. 293—296 1999
[19] Z. Jin et al., “Nickel induced crystallization of amorphous silicon films,” JJAP, vol. 84, p. 194, 1998.
[20] M. Wang, et al. “Anisotropic conduction behavior in metal-induced laterally crystallized polycrystalline silicon thin films,” Appl. Phys. Lett., vol. 76, p. 448, 2000
[21] M. Wang, et al. “The effects of high temperature annealing of metal-induced laterally crystallized polycrystalline silicon,” IEEE Trans. Electron Devices, vol. 47, pp. 2061—2067, Nov. 2000
[22] Shimoda, T. et al. ”Surface free technology by laser annealing (SUFTLA)” IEDM pp. 289 -292 1999
[23] Schmolke R, et al. “On the impact of nanotopography of silicon wafers on post-chemical mechanical polished oxide layers,” Journal of the Electrochemical Society, vol.149, no.4, pp.G257-65, April 2002
[24] H. Robbin, et al. “chemical etching in silicon. Ⅱ. The system HF, HNO3, and H2O,” J. Electrochemical Soc. 106, 505 1960
[25] Melcher RL. “LCoS microdisplay technology and applications,” Society of Information Display, pp.1069-1071 2000
[26] S. D. Theiss, et al., “Polysilicon Thin Film Transistors Fabricated at 100℃ on a Flexible Plastic Substrate,” IEEE Electron Device Meeting, pp. 257, 1998
[27] D.J. Gundlach, et al. “High-Mobility, Low Voltage Organic Thin Film Transistors,” IEEE Electron Devices Meeting pp.111 1999
[28] M.J. Lee, et al. “Thin film transistors for displays on plastic substrates” Solid State Electronics vol. 44 pp. 1431 to 1434, 2000
[29] S. D. Theiss et al. “Amorphous silicon thin-film transistors on steel foil substrates,” IEEE Electron Device Letters, vol. 17, pp. 578—580, 1996.
[30] H. Gleskova, et al. “Flexible glass substrates with via holes for TFT backplates,” Dig. Tech. Papers, pp. 105—108 Nov. 1996
[31] H. Gleskova, et al. “Electro- photographically patterned thin-film silicon transistors,” IEEE Electron Device Lett., vol. 17, pp. 264—266, 1996.
[32] H. Gleskova, et al. “Via hole technology for thin-film transistor circuits,” IEEE Electron Device Lett., vol. 18, pp. 523—525, 1997.
[33] C. C. Wu, et al. “Organic LED’s integrated with a-Si TFT’s on lightweight metal substrates,” Society of Information Display, pp. 67—70 1997
[34] Ming Wu et al. “High temperature polycrystalline silicon thin film transistor on steel substrates” IEDM Technical Digest International, pp. 119 -122 1999
Chapter 2
[1] Chiang C-S, et al. “Electrical instability of hydrogenated amorphous silicon thin-film transistors for active-matrix liquid-crystal displays,” JJAP vol.37, no.9A, pp.4704-10 Sept. 1998
[2] Kinoshita H, et al. “High-resolution AMLCD made with a-Si:H TFTs and with an Al-gate and IZO last structure,” Society of Information Display, pp.736-41, 1999
[3] Koichi Kanzaki et al., “Direction of Low-Temperature p-Si Technology,” Society of Information Display Digest, pp. 242 — pp. 245, 2001
[4] Cheol-Min Parket al. “A four terminal polycrystalline silicon TFT for AMLCD application,” Society of Information Display Digest, pp. 953-956 1998
[5] Mark Stewart et al., “Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp.845, 2001
[6] I. W. Wu, et al. “Low temperature poly-Si TFT technology for AMLCD application,” AMLCD, pp. 7—10, 1995
[7] T. Serikawa, et al. “Low temperature fabrication of high mobility poly-Si TFT’s for large-area LCD’s,” IEEE Trans. Electron Devices, vol. 36, pp. 1929—1933, 1989
[8] J. Jang, et al. “Low temperature polycrystalline silicon thin film transistors” Elsevier Science Ltd vol. 51, no. 4, pp. 769 — 775, 1998
[9] I. W. Wu, et al. “Poly-Si TFT LCD technology and prospect of future displays,” EDMS, pp. 309—312, 1997
[10] Shengdong Zhang, et al. “Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass,” IEEE Transactions on Electron Devices, vol.47, no.3, pp.569-75, March 2000
[11] Z. Jin et al., “Nickel induced crystallization of amorphous silicon films,” JJAP, vol. 84, p. 194, 1998.
[12] M. Wang, et al. “Anisotropic conduction behavior in metal-induced laterally crystallized polycrystalline silicon thin films,” Appl. Phys. Lett., vol. 76, p. 448, 2000
[13] G. K. Giust, et al. “Low-temperature poly-silicon thin-film transistors fabricated from laser-processed puttered-silicon films,” IEEE Electron Device Lett., vol. 19, pp. 43—344, 1998
[14] Schmolke R, et al. “On the impact of nanotopography of silicon wafers on post-chemical mechanical polished oxide layers,” Journal of the Electrochemical Society, vol.149, no.4, pp.G257-65, April 2002
[15] Hocheng H, et al. “Modeling and experimental analysis of the material removal rate in the chemical mechanical planarization of dielectric films and bare silicon wafers,” Journal of the Electrochemical Society, vol.148, no.10, pp.G581-G586, Oct. 2001
[16] Sooriakumar K, et al. “A comparative study of wet versus dry isotropic etch to strengthen silicon micromachined pressure sensor,” Electrochem. Soc. pp. 259-265, 1995
[17] H. Robbin, et al. “chemical etching in silicon. Ⅱ. The system HF, HNO3, and H2O,” J. Electrochemical Soc. 106, 505 1960
Chapter 3
[1] Sandoe JN. “AMLCD on plastic substrates,” SID Vol. 29 Soc. pp.293-6 1998
[2] S. D. Theiss et al., “Polysilicon Thin Film Transistors Fabricated at 100℃ on a Flexible Plastic Substrate,” IEEE Electron Device Meeting, pp. 257, 1998
[3] Carey PG, et al. “Polysilicon thin film transistors fabricated at 100 degrees C on a flexible plastic substrate,” IEEE Annual Device Research Conference Digest pp.58-9 1997
[4] Shannon JM, et al. “TFDs for high quality AMLCD on low temperature plastics,” AMLCD pp.49-52 1996
[5] M.J. Lee, et al. “Thin film transistors for displays on plastic substrates” Solid-State Electronics vol. 44, pp. 1431 - 1434 2000
[6] D.J. Gundlach, et al. “High-Mobility, Low Voltage Organic Thin Film Transistors,” IEEE Electron Devices Meeting pp.111 1999
[7] Hocheng H, et al. “Modeling and experimental analysis of the material removal rate in the chemical mechanical planarization of dielectric films and bare silicon wafers,” J. of the Electrochemical Society, vol.148, no.10, pp.G581-G586, Oct. 2001
[8] H. Robbin, et al. “chemical etching in silicon. Ⅱ. The system HF, HNO3, and H2O,” J. Electrochemical Soc. 106, 505 1960
[9] H. Seidel, et al. “Anisotropic etching of crystalline silicon in alkaline solution. I. Orientation dependence and behavior of Passivation layers,” J. Electrochemical Soc., 137, 3612 1990
[10] H. Muraoka, et al. “Controlled preferential etching technology,” Electrochemical Society pp.327 1973
[11] Q.Y.TONG “Semiconductor Wafer Bonding: Science and Technology,” 1999

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