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研究生:林新富
研究生(外文):Lin Hsin-Fu
論文名稱:利用汲極端包覆性植入結構改善快閃記憶體的性能與可靠性之研究
論文名稱(外文):Performance and Reliability Improvement of Flash EEPROM with Pocket-Implanted Drain Structure
指導教授:莊紹勳
指導教授(外文):Steve S. Chung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:72
中文關鍵詞:快閃記憶體寫入抹除擾動持久性保存
外文關鍵詞:flashprogramerasedisturbenduranceretention
相關次數:
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  • 收藏至我的研究室書目清單書目收藏:1
近年來,快閃式記憶體(Flash memory)已成為非揮發性記憶體之主流,它被廣泛地應用於大量資料儲存上,例如:數位相機與手提電腦等可攜式電子產品。在快閃式記憶體元件的設計上,高效能(performance)以及高可靠性(reliability)為兩個最重要的考量因素。要達成這個目的,最直接/有效的方法乃是建構一個新的操作模式,同時並最佳化其元件結構。本論文即設計了一個新的快閃式記憶體元件寫入方式- 它利用汲極崩潰熱電子注入模式達成寫入之目的,除可符合效能/可靠性兩大要求外,同時並可低電壓操作。
在本論文中,吾人利用基極偏壓增強汲極累增崩潰熱電子注入(AHE),設計出一種可用於低功率及高效能快閃記憶體的寫入方式。同時,吾人在靠近汲極端且遠離矽氧化層-通道(oxide-channel)界面之適當深度,植入高濃度的硼(pocket implantation),使汲極及基極接面更容易發生接面崩潰(junction breakdown),使元件可低電壓操作且可提昇了元件的寫入效能。在可靠性部分,發生崩潰的位置遠離矽氧化層-通道界面,所以可以有效的抑制介面狀態(interface state, Nit)的產生。同時,因為當代製程技術之提昇,可將高濃度的硼離子精準植入汲極-基極接面間適當的位置,這可在減低元件寫入時汲極-基極接面崩潰傷害。此外,從本論文所得之研究結果顯示,這個新的低電壓操作的寫入方法,無論是閘極擾動(gate disturb)或汲極擾動(drain disturb)都比目前最廣泛使用的通道熱電子注入(CHE)優異。因此,此一新式的快閃式記憶元件操作模式結合最佳化之結構,將可用於設計下一世代高效能、高可靠性、和低電壓操作之快閃式記憶體。

Recently, the flash memory has become one of the main stream of nonvolatile semiconductor memory product, which has been widely used for mass data storage, such as the digital cameras and hand-held computer as a portable mass storage. For the design of flash memories, the performance and reliability are still the major concerns, in which two approaches are usually employed, one is to develop a novel cell structure, and the other one is to develop a different operation scheme. The most effective way to achieve high performance and low operation voltage requirements are the two approaches as mentioned above. The objective of this thesis is to design an appropriate structure based on the existing ETOX cell by a combination of a new programming scheme.
In this thesis, first, we proposed a programming scheme, which is called Substrate Bias Enhanced Drain Avalanche Breakdown Hot-Electron (AHE) Injection, for low voltage, low power, and high performance flash memory application,. For the requirement of the low voltage operation, we implant a highly doped boron at the drain side (Pocket Implantation) and control a proper depth from the silicon and silicon dioxide interface to make the cell reach breakdown easily. In addition, this scheme has high programming speed, and meets the requirement of high performance operation. In the term of cell reliability, the interface state (Nit) generation can be suppressed since the position of avalanche breakdown is away form at the silicon and silicon dioxide interface. Also, with the improvement of process technology, reduction of drain and substrate junction damage during programming can be achieved by exactly controlling the position of highly doped implanted boron. In terms of the reliability, gate disturb and drain disturb are greatly reduced as a result of a low voltage operation. The present scheme is better than widely used channel hot-electron (CHE) injection. As a whole, the AHE programming scheme based on the improved ETOX cell structure can be well-suited for the next generation high performance and high reliability flash memory applications.

Contents
Chinese Abstract i
English Abstract iii
Acknowledgements v
Contents vi
Figure Captions viii
Table Captions xii
List of Symbols xiii
Chapter 1 Introduction 1
Chapter 2 Device Fabrication and Experimental Setup 4
2.1 Device Fabrication 4
2.2 Experimental Setup 7
Chapter 3 Extraction of Basic Device Parameters 12
3.1 Threshold Voltage Determination 12
3.2 The Extraction of Coupling Ratio 12
3.3 Floating Gate Potential and Gate Current
Measurement 14
Technique
Chapter 4 Cell Performance and Reliability 20
4.1 Introduction 20
4.1.1 AHE and CHE Injection Mechanisms 20
4.1.1.1 AHE Injection Mechanism 20
4.1.1.2 CHE Injection Mechanism 23
4.1.2 Split and Bias Conditions 23
4.2 Cell Performance 24
4.2.1 Programming Speed 24
4.2.2 Power Consumption 35
4.3 Cell Reliability 37
4.3.1 Program Disturb 37
4.3.1.1 Gate Disturb 37
4.3.1.2 Drain Disturb 38
4.3.1.3 Read Disturb 38
4.3.1.4 Substrate Disturb 39
4.3.2 Endurance Characteristics 44
4.3.3 Data Retention Characteristics 44
4.3.4 Damage Evaluation of AHE and CHE
programming 47
Schemes
4.3.4.1 GIDL and GIBL Current 47
4.3.4.2 Subthreshold and Transconductance
(Gm) 48
Characteristics
4.3.4.3 Gate Injection Current Degradation 49
4.3.4.4 Gated Diode and Stress Induced
Leakage 49
Current (SILC)
4.3.4.5 Junction Leakage Current 50
4.4 Performance and Reliability Analysis by 2-D
Device Simulation 58
4.4.1 Device Simulation for AHE Programming Scheme 58
4.4.2 Device Simulation for CHE Programming Scheme 59
4.4.3 Reliability Analysis for AHE and CHE
Programming 64
Schemes
Chapter 5 Summary and Conclusion 66
References

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