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研究生:許勝福
研究生(外文):HSU,SHENG-FU
論文名稱:一種製造於部分空乏型矽在絕緣層上之短通道金氧半場效電晶體的二維解析模式
論文名稱(外文):A 2-D Analytic Model for Short-Channel MOSFET Fabricated on Partially-Depleted SOI
指導教授:吳慶源
指導教授(外文):Ching-Yuan wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:73
中文關鍵詞:金氧半場效電晶體部分空乏型
外文關鍵詞:SOIPartially-DepletedMOSFET
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摘要
在深次微米積體電路中,由於具有低操作功率、防止輻射干擾、較小的次臨界變動及非常快的元件操作速度等等吸引人的優點,因此矽在絕緣層上之金氧半場效電晶體已被期盼可與傳統式金氧半場效電晶體一較高下.然而,由於完全空乏型矽在絕緣層上之金氧半場效電晶體受制於可能因為晶圓表面上矽導體薄層控制不均勻所造成的起始電壓之變動,因此部分空乏型矽在絕緣層上之金氧半場效電晶體在現代矽在絕緣層上之金氧半場效電晶體技術中已越來越受到大家重視.
在本篇論文中,我們討論並推導一種包含起始電壓和電流-電壓特性模型之短通道部分空乏型矽在絕緣層上之金氧半場效電晶的二維解析模式.此外,由於矽在絕緣層上之金氧半場效電晶體元件中具有非常差的功率散逸特性,因此一種名為“自我積熱效應”的嚴重缺點也將藉由二維數值分析模擬器(MEDICI)的幫助之下來得到推導及驗證.最後,本篇論文的主要貢獻及一些未來仍須做進一步的努力研究方向將在本篇論文的最後提出.

Abstract
The SOI (silicon-on-insulator) MOSFET is expected to become competitive with conventional bulk MOSFET in deep sub-micrometer integrated circuits owing to its attractive device advantages such as low operation power﹐radiation hardness﹐smaller subthreshold swing﹐and very high speed performances﹐etc﹒Fully—Depleted(FD) SOI MOSFET﹐however﹐suffers from the thin silicon film across the wafer can not be controlled uniformly which results in the threshold voltage being varied dependent on the unexpected manufacturing processes variations﹒For this reason﹐a growing interests of the Partially-Depleted(PD) SOI MOSFET is the current trend in the modern SOI technology﹒
In this thesis﹐a 2-D analytic model of the short-channel PD SOI MOSFET includes the threshold voltage and I-V characteristics will be derived and discussed﹒Moreover﹐a extremely serious drawback of the SOI devices resulting from the poor power dissipation named“Self-Heating-Effect”will be modeled and verified by the aid of the 2-D numerical simulator(MEDICI)﹒Finally﹐the major contributions of this thesis and some future researches deserved further efforts are proposed﹒

Abstract III
Acknowledgements V
Contents VI
Table Captions IX
Figure Captions X
Nomenclature XII
Chapter 1 Introduction
1-1 General Introduction 1
1-2 Organization of the Thesis 1
Chapter 2 A Simple Quasi-2D Threshold-Voltage Model for Partially- Depleted Short-Channel SOI MOSFET
2-1 Introduction 3
2-2 The Derivations of Threshold-Voltage Model 4
2-3 Model Verification and Its Modification 8
2-4 Conclusions 9
Chapter 3 The Analytic I-V Model for Partially-Depleted Short- Channel SOI MOSFET
3-1 Introduction 11
3-2 The Analytic I-V Model 12
(A) The Derivation of DIBL Factor 12
(B) The Drain Current Model for PD SOI MOSFET Operated in the Liner Region 12
(C) The Drain Saturation Voltage and Saturation Current 14
(D) The Channel-Length Modulation Factor 14
(E) The Drain current Model for PD SOI MOSFET Operated in the Saturation Region 18
3-3 Verification 19
3-4 Conclusions 20
Chapter 4 The Analytic I-V Model Including the Self-Heating Effect of PD SOI MOSFET
4-1 Introduction 21
4-2 The Analytical I-V Model Including the Self-Heating Effect 22
(A) The Basic Analysis 22
(B) The Drain Saturation Voltage and Saturation Current 24
(C) The Drain Current Model Considering the Self-Heating Effect for PD SOI MOSFET Operated in the Liner Region
26
(D) The Drain current Model Considering the Self-Heating Effect for PD SOI MOSFET Operated in the Saturation Region 27
4-3 Verification 28
4-4 Conclusions 29
Chapter 5 Conclusions
5-1 Major Contributions of the Thesis 31
5-2 Proposed Future Researches 32
Appendices
References
Table
Figures
Vita

References
[1] Mike S. L. Lee﹐Bernard M. Tenbroek﹐and William Redman-White et. al.﹐”A Physically Based Compact Model of Partially Depleted SOI MOSFETs for Analog Circuit Simulation﹐”IEEE Jour. of Solid-State Circuits﹐Vol. 36﹐No. 1﹐pp. 110﹐Jan. 2001﹒
[2] M. Youssef Hammad and Dieter K. Schroder﹐”Analytical Modeling of the Partially-Depleted SOI MOSFET﹐”IEEE Trans. on Electron Devices﹐Vol. 48﹐No. 2﹐pp. 252﹐Feb. 2001﹒
[3] Pin Su﹐Samuel K. H. Fung and Stephen Tang et. al.﹐“BSIMPD : A Partial-Depletion SOI MOSFET Model for Deep-Submicron CMOS Designs﹐”IEEE Custom Integrated Circuits Conference﹐pp. 197﹐2000﹒
[4] J. -P. Colinge﹐”Silicon-on-insulator Technology : Materials to VLSI﹐2nd ed﹐”Kluwer Academic : Boston﹐1997﹒
[5] Lisa T. Su﹐James E. Chung﹐Dimitri A. Antoniadis﹐Kenneth E. Goodson﹐and Markus I. Flik﹐”Measurement and Modeling of Self-Heating in SOI NMOSFET's”IEEE Trans. on Electron Devices﹐Vol. 41﹐No. 1﹐pp. 69﹐Jan. 1994﹒
[6] G.-S. Huang and C.-Y. Wu﹐”An Analytic Saturation Model for Drain and Substrate Currents of Conventional and LDD MOSFET's﹐”IEEE Trans. on Electron Devices﹐Vol. ED-37﹐No. 7﹐pp. 1667﹐July. 1990﹒
[7] T. Toyabe and S. Asai﹐”Analytic Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis﹐”IEEE Trans. on Electron Devices﹐Vol. 26﹐No. 4﹐pp. 453﹐Apr. 1979﹒
[8] P.-S. Lin and C.-Y. Wu﹐”A New Approach to analytically Solving the 2-D Poisson's Equation and its application in Short-Channel MOSFET Modeling﹐”IEEE Trans. on Electron Devices﹐Vol. 34﹐No. 9﹐pp. 1947﹐Sept. 1987﹒
[9] J.-Y. Guo and C.-Y. Wu﹐”2-D Analysis and Complete New Analytic Models for Short- Channel Thin Film MOSFET's﹐”1994 Ph.D. Thesis﹐Institute of Electronics﹐National Chiao-Tung University﹒
[10] W.-Y. Hsieh and C.-Y. Wu﹐”A 2-D Analytic Model for Short-Channel SOI MOSFET﹐”2001 MS. Thesis﹐Institute of Electronics﹐National Chiao-Tung University﹒
[11] C.-Y. Wu and Y.-W. Daih﹐”An Accurate Mobility Model for The I-V Characteristics of n-Channel Enhancement-Mode MOSFET's with Single-Channel Boron Implantation﹐”Solid-State Electron﹐Vol. 28﹐No. 12﹐pp. 1271﹐Dec. 1985﹒
[12] Yu-Guang Chen﹐Shyh-Yih Ma and James B. Kuo et. al. ”An Analytical Drain Current Model Considering Both Electron and Lattice Temperatures Simultaneously for Deep Submicron Ultrathin SOI NMOS Devices with Self-Heating﹐” IEEE Trans. on Electron Devices﹐Vol. 42﹐No. 5﹐pp. 899﹐May. 1995﹒
[13] Man-Chun Hu and Sheng-Lyang Jang﹐”An Analytical Fully-Depleted SOI MOSFET Model Considering the Effects of Self-Heating and Source/Drain Resistance﹐” IEEE Trans. on Electron Devices﹐Vol. 45﹐No. 4﹐pp. 797﹐April. 1998﹒
[14] Yuhua Cheng and Tor A. Fjeldly﹐”Unified Physical I-V Model Including Self-Heating Effect for Fully Depleted SOI/MOSFET's﹐” IEEE Trans. on Electron Devices﹐Vol. 43﹐No. 8﹐pp. 1291﹐August. 1996﹒
[15] J. B. Roldan﹐F. Gamiz﹐J. A. Lopez-Villanueva and P. Cartujo-Cassinello﹐”Deep Submicronmeter SOI MOSFET Drain Current Model Including Series Resistance﹐Self-Heating and Velocity Overshoot Effects﹐” IEEE Trans. on Electron Devices﹐Vol. 21﹐No. 5﹐pp. 239﹐May. 2000﹒
[16] L. T. Su﹐D. A. Antoniadias﹐N. D. Arora﹐B. S. Doyel and D. B. Karkauer﹐”SPICE Model and Parameters for Fully-Depleted SOI MOSFET's Including Self -Heating﹐”IEEE Electron Device Lett.﹐Vol. 15﹐pp.374﹐1994﹒
[17] Sharma﹐D. K. and Ramanathan﹐K. V.﹐”Modeling Thermal Effects on MOS I/V Characteristics﹐”IEEE Electron. Dev. Lett.﹐EDL-4﹐(10)﹐pp. 362﹐1983﹒
[18] L. J. McDaid﹐S. Hall﹐P. H. Mellor and W.Eccleston﹐”Physical Origin of Negative Differential Resistance in SOI Transistors﹐”Electron. Lett.﹐Vol. 25﹐pp. 827﹐1989﹒
[19] Dinesh Sharma﹐Jacques Gautier and Gerard Merckel﹐”Negative Dynamic Resistance in MOS Devices﹐”IEEE Jour. of Solid-State Circuits﹐Vol. SC-13﹐No. 3﹐pp. 378﹐June. 2001﹒

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