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研究生:李健銘
研究生(外文):Chien-Ming Lee
論文名稱:適用於射頻積體電路之靜電放電防護設計
論文名稱(外文):ESD PROTECTION DESIGN FOR RADIO FREQUENCY CIRCUITS
指導教授:柯 明 道
指導教授(外文):Ming-Dou Ker
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:84
中文關鍵詞:靜電放電射頻積體電路二極體LC共振
外文關鍵詞:ESDRFICDiodeLC tank
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本論文針對靜電放電防護電路的寄生效應對射頻積體電路特性的影響,分成三部份來探討。本論文的第一部份,利用雙埠GSG實驗量測0.25微米CMOS製程中的靜電放電防護元件對射頻訊號之增益和雜訊的影響。在不同的參數變化下,比較其靜電放電防護能力與增益損耗和雜訊變化的關係,確認靜電放電防護電路對射頻訊號的影響大小。最後在諸多的比較資料中,選擇最適合應用在射頻積體電路中的靜電放電防護元件。
本論文的第二部份,提出適用在射頻積體電路的靜電放電保護電路,其人體靜電放電模式之靜電放電耐受度高達8仟伏特。藉著加入一電源線間有效的靜電放電箝制電路在射頻積體電路中,使得射頻輸入端的靜電放電元件操作在順向導通區,而非傳統的崩潰區。藉此可讓射頻輸入端的靜電放電元件所需之元件面積大幅地降低,來減少對輸入射頻訊號的負載效應。這個設計已經成功地應用在900MHz的射頻接收端,並且在具有上層厚金屬的0.25微米CMOS製程中實際晶片驗證,實驗結果顯示其人體靜電放電模式下之靜電放電耐受度可高達8仟伏特以上。
本論文的第三部份,提出一新的射頻靜電放電防護電路設計。利用LC共振串聯來阻絕射頻訊號因靜電放電防護電路所引起的損耗以及雜訊來源。由於電感是由最上層的厚金屬所環繞而成,所以其可成為非常好的靜電放電電流的導通路徑。實驗結果顯示此一射頻靜電放電防護架構對射頻訊號的影響優於傳統的二極體靜電放電防護電路。在未來射頻操作頻率越加增高的趨勢之下,此設計將成為更適合的射頻靜電放電防護電路。
本論文之研發成果,已經提出三項美國專利申請,並已發表一篇研討會論文於2002 IEEE RFIC Symposium 國際研討會中,另有一篇論文已被2002 VLSI Design/CAD Symposium研討會所接受,第三篇論文並已投稿2002 Taiwan ESD Conference。

To reduce the parasitic effect of the ESD protection circuit devoted to RF integrated circuits, there are three major designs proposed in this thesis. In the first part, the two-port GSG measurement setup in the radio-frequency region (~GHz) is used to measure the power gain S21 and noise figure from different ESD devices in 0.25-µm CMOS process. Therefore, we can get the relationship between RF performance and ESD level among different ESD devices. The most suitable ESD device for RF application can be selected from the measured data.
The second part presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of 8kV. By including a turn-on efficient power-rails ESD clamp circuit into the RF circuit, the ESD protection devices of the RF input pin can be operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in a 0.25-µm CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as 8kV under the HBM ESD test.
In the third part, a new structure of ESD protection circuit for RF application is proposed. The series LC-tank is used to block the signal loss and noise figure from the ESD protection devices to the RF input pin. The inductor is made by the top thick metal, which is suitable to conduct ESD current. The experimental results have shown that the RF performance of ESD protection circuit with LC-tank is superior to that of the traditional ESD protection circuit with double diodes. The ESD protection circuit with LC-tank is more suitable for RF application when the operation frequency becomes higher.
The research results of this thesis have been applied 3 U.S. patents. Moreover, the contents of this thesis had also published three conference papers. One paper had been presented in the 2002 IEEE RFIC Symposium, the second paper has been accepted by the 2002 VLSI Design/CAD Symposium, and the third paper has been submitted to 2002 Taiwan ESD Conference.

ABSTRACT (CHINESE)
ABSTRACT (ENGLISH)
ACKNOWLEDGEMENTS
CONTENTS
TABLE CAPTIONS
FIGURE CAPTIONS
CHAPTER 1 INTRODUCTION
1.1 Background
1.2 Thesis Organization
CHAPTER 2 INVESTIGATION ON DIFFERENT DIODE STRUCTURES AS ESD PROTECTION IN RF APPLICATION
2.1 Diodes
2.1.1 STI Diode
2.1.2 Poly-gate Diode
2.2 Experimental Results
2.2.1 Device Characteristic
2.2.2 Power Gain S21
2.2.3 Noise Figure
2.2.4 ESD Robustness and TLPG I-V Curves
2.2.5 Optimization of Diode
2.3 Summary
FIGURES of Chapter2
CHAPTER 3 THE STATE OF ART ESD PROTECTION DESIGN FOR 900-MHZ RF RECEIVER
3.1 ESD Protection Design For RF Receiver
3.2 Experimental Results
3.2.1 ESD Test Results
3.2.2 RF Performance
3.3 Summary
TABLES of Chapter3
FIGURES of Chapter3
CHAPTER 4 A NOVEL LC-TANK ESD PROTECTION DESIGN FOR RF APPLICATION
4.1 LC-Tank RF ESD Protection Design
4.1.1 RF Operation
4.1.2 ESD Operation
4.2 Experimental Results
4.2.1 Power Gain S21
4.2.2 Noise Figure
4.2.3 Turn On Verification
4.2.4 ESD Robustness and TLPG I-V Curves
4.3 Discussion and Summary
TABLES of Chapter4
FIGURES of Chapter4
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS
5.1 Main Results Of This Thesis
5.2 Future Works
REFERENCES
VITA
PUBLICATION LIST

[1] E. Morifuji, H. S. Momose, T. Oghuro, T. Yoshitome, H. Kimijima, F. Matsuoka, M. Linugawa, Y. Katsumata, and H. Iwai, “Future perspective and scaling down roadmap for RF CMOS”, Dig. Tech. Papers VLSI Symp., 1999, pp. 163-164.
[2] T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashbum, R. Aggarwal, A. Singh, Zhang Xin, G. Misium, A. L. Esquivel, M. Jain, S. Madan, T. Breedijk, A. Singh, G. Thakar, G. Shinn, B. Riemenscheider, S. O’Brien, D. Frystak, J. Kittl, and Amerase, “0.18 /spl mu/m CMOS technology for high-performance, low-power, and RF applications”, Dig. Tech. Papers VLSI Symp., 1997, p. 13-14.
[3] A. Rofougan, J. Y. Chang, M. Rofougan, and A. A. Abidi, “A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver”, IEEE J. Solid State Circuits, vol. 31, pp. 880-889, 1996.
[4] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, Wiley, 1995.
[5] J. E. Vinson and J. J. Liou, “ESD protection techniques for semiconductor devices,” in Proc. of Int. Conf. on Microelectronics, 2000, pp. 311-321.
[6] MIL-STD-883E method 3015.7, Military Standard Test Methods and Proc. for Microelectronics, Dept. of Defense, Washington D.C., U.S.A., 1996.
[7] Electrostatic Discharge (ESD) Sensitivity Testing — Human Body Model (HBM), test method A114-A, EIA/JEDEC Standard, Electronic Industries Association, 1997.
[8] ESD Association Standard Test Method for Electrostatic Discharge Sensitivity Testing: Human Body Model — Component Level, ESD STM5.1, ESD Association, NY., 1998.
[9] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, “Investigation on different ESD protection strategies devoted to 3.3V RF applications (2 GHz) in a 0.18µm CMOS process”, Proc. of EOS/ESD Symp., 2000, pp. 251-259.
[10] R. Velghe, P. Vreede, and P. Woerlee, “Diode network used as ESD protection in RF applications”, Proc. of EOS/ESD Symp., 2001, pp. 337-345.
[11] G. Gramegna, M. Paparo, P.G. Erratico, and P. De Vita, “A Sub-1-dB NF 2.3-kV ESD-protected 900-MHz CMOS LNA”, IEEE J. Solid-State Circuits, vol.36, pp.1010-1017, July 2001.
[12] P. Leroux, J. Janssens, and M. Steyaert, “A 0.8 dB NF ESD-protected 9 mW CMOS LNA”, ISSCC Dig. of Tech. Papers, 2001, pp.410-411.
[13] B. Kleveland and T. H. Lee, “Distributed ESD protection for high-speed integrated circuits”, USA Patent 5969929, Oct. 1999.
[14] B. Kleveland, T. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, “Distributed ESD protection for high-speed integrated circuits”, IEEE Electron Device Letters, vol.21, pp.390—392, Aug. 2000.
[15] C. Ito, K. Banerjee, R. W. Dutton, “Analysis and design of ESD protection circuits for high-frequency/RF applications”, Proc. of IEEE Int. Symp. on Quality Electronic Design, 2001, pp. 117—122.
[16] C.-Y. Chang and M.-D. Ker, “On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process”, in Proc. of Int. Symp. on VLSI Technology, Systems, and Application, 2001, pp. 240-243.
[17] S. Daniel and G. Krieger, “Process and design optimization for advanced CMOS I/O ESD protection devices,” in Proc. of EOS/ESD Symp., 1990, pp. 206—213.
[18] S. G. Deebe, “Methodology for layout design and optimization of ESD protection transistors,” in Proc. of EOS/ESD Symp., 1996, pp. 265—275.
[19] C. Duvvury and C. Diaz, “Dynamic gate coupling of nMOS for efficient output ESD protection,” in Proc. IRPS, 1992, pp. 141—150.
[20] M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, “Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,” IEEE Trans. VLSI Syst., vol. 4, pp. 307—321, Sept. 1996.
[21] C. Richier, N. Maene, G. Mabboux, and R. Bellens, “Study of the ESD behavior of different clamp configurations in a 0.35um CMOS technology,” in Proc. of EOS/ESD Symp., 1997, pp. 240—245.
[22] M.-D. Ker, T.-Y. Cheng, C.-Y. Wu, H. Tang, K.-C. Su, and S.-W. Sun, “Novel input ESD protection circuit with substrate-triggering technique in a 0.25-um shallow-trench-isolation CMOS technology,” in Proc. IEEE Int. Symp. Circuits and Systems, 1998, pp. 212—215.
[23] H. G. Feng, K. Gong, and A. Z. Wang, “A novel on-chip electrostatic discharge protection design for RF ICs,” in Journal of Microelectronics, pp. 189-195, 2001.
[24] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, vol. 46, pp. 173—183, 1999.
[25] A. Amerasekera, L. van Roozendaal, J. Abderhalden, J. Bruines, and L. Sevat, “An analysis of low voltage ESD damage in advanced CMOS process,” in Proc. of EOS/ESD Symp., 1990, pp. 143-150.
[26] E. Abou-Allam, J. J. Nisbet, and M. C. Maliwpaard, “Low-voltage 1.9-GHz front-end receiver in 0.5-µm CMOS technology,” IEEE J. of Solid-State Circuits, vol. 36, pp. 1434-1443, 2001.
[27] P. Leroux and M. Steyaert, “High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection,” Electronics Letters, vol. 37, pp. 467-469, 2001.
[28] EOS/ESD Standard for ESD Sensitivity Testing, S 5.1, EOS/ESD Association, N.Y., 1993.
[29] M.-D. Ker, T-Y. Chen, C-Y. Wu, and H-H. Chang, “ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1194-1199, 2000.

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