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研究生:廖大舜
研究生(外文):Tai-Shun Liao
論文名稱:矽鍺在複晶矽薄膜電晶體上的應用
論文名稱(外文):Applications of SiGe on The Polycrystalline Silicon Thin-Film Transistors
指導教授:張俊彥
指導教授(外文):Chun-Yen Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:66
中文關鍵詞:薄膜電晶體矽鍺間隙壁選擇性矽鍺
外文關鍵詞:TFTSiGe spacerselective SiGe
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在本論文中,我們提出一個矽鍺間隙壁的新結構來降低複晶矽薄膜電晶體的漏電流。我們利用超高真空化學氣相沉積(Ultra High Vacuum Chemical Vapor Deposition, UHVCVD)矽鍺在複晶矽表面沉積但在氧化矽表面不沉積的特性,選擇性的在複晶矽閘級側邊橫向沉積矽鍺間隙壁(SiGe spacer)。此製成具有製程簡單、製成溫度與傳統低溫複晶矽薄膜電晶體接近和矽鍺間隙壁是自我對準等優點。由實驗結果,我們發現這個新結構的矽鍺間隙壁的確能有效降低在汲極端空乏區的電場。與傳統的複晶矽薄膜電晶體比較之下,我們的新結構能降低漏電流的產生、使轉折效應不明顯並且在元件可靠度方面也有顯著的改善。
另外為了整合主動式液晶顯示器上的周邊電路,複晶矽薄膜電晶體必須要有較大的驅動的電流跟較高的崩潰電壓。而使用超薄通道元件雖然可以得到較大的驅動電流但是卻會伴隨著較大的源極、汲極接觸電阻、較大的寄生串聯電阻還有較小的崩潰電壓等等會降低元件性能的問題發生。為了克服這些問題,我們提出一個利用選擇性矽鍺沉積來製作薄通道但是卻有較厚源極、汲極元件的新製程.與先前製作薄通道但是卻有較厚源極、汲極元件的製程比較之下,此製成具有不需額外光罩、自我對準製程和與傳統複晶矽薄膜電晶體製成相容的優點.由實驗結果,我們的新結構能提高導通電流、具有較大的崩潰電壓、降低源極、汲極的電阻和降低漏電流的特性。

In this dissertation, we proposed two different novel polycrystalline-silicon thin-film transistors (poly-Si TFTs) to improve device performance. Firstly, a new SiGe spacer with lightly-doped drain (LDD) structure was fabricated to reduce the anomalous leakage current of poly-Si TFTs. The SiGe spacer was selectively grown in ultra-high vacuum chemical vapor deposition (UHVCVD) system at 550°C. The resultant SiGe spacer TFTs features a self-aligned LDD region and no additional masks are required, which is ideally suitable for AMLCD applications. Our experimental results show that device performance such as kink-effect, leakage current and reliability are improved with SiGe spacer TFTs, compared to conventional counterparts.
To integrate peripheral circuits on AMLCD, higher drive current and breakdown voltage are necessary. To this end, another novel TFTs with SiGe raised source/drain TFTs (SiGe RSD TFTs) was proposed. The SiGe RSD TFTs feature an ultra-thin channel and a thick S/D region. Ultra thin channel is beneficial for higher drive current and lower leakage current. However, ultra thin film suffers from a poor S/D resistance, which degrades device performance. In our work, SiGe raised S/D regions were selectively deposited in UHVCVD system to overcome this problem. With SiGe RSD TFTs, device performances such as turn-on current, leakage current, and breakdown voltage are superior to those with conventional TFTs. Moreover, the process is simple and no additional masks are necessary, which is consistent with conventional fabrications.

Chinese Abstract Ⅰ
English Abstract Ⅱ
Acknowledgement (Chinese) Ⅲ
Contents Ⅳ
Table Captions Ⅵ
Figure Captions Ⅶ
Chapter 1 Introduction 1
1.1 Overview of Polycrystalline Silicon Thin Film Transistor Technology 1
1.2 Motivation 2
1.2-1 Leakage Current of Poly-Si TFTs 3
1.2-2 Ultra Thin Channel Device
1.3 Thesis outline 4
Chapter 2 Poly-Si Films Preparation by LPCVD and UHVCVD & Method
Of Device Parameter Extraction 5
2.1 Poly-Si Films Preparation by LPCVD and UHVCVD 5
2.1-1 Introduction 5
2.2-2 The Environment for Depositing Thin Channel Film 6
2.1-3 Selective Deposition of Poly-SiGe Film by UHVCVD System 6
2.1-4 Description of the UHVCVD System 7
2.2 Method of Device Parameter Extraction 7
2.2-1 Determination of Threshold Voltage 8
2.2-2 Determination of Subthreshold Swing 8
2.2-3 Determination of Field Effect Mobility 9
2.2-4 Determination of On/Off Current Ratio 10
Chapter 3 A Novel Polycrystalline Thin-Film Transistor with SiGe Spacer 11
3.1 Introduction 11
3.2 Fabrication of SiGe Spacer Poly-Si TFT 12
3.3 Result and Discussion 14
3.3-1 Device Characteristic of SiGe Spacer Poly-Si TFTs 14
3.3-2 Hot-Carrier Reliability of SiGe Spacer Poly-Si TFTs 15
3.4 Summary 16
Chapter 4 A Novel SiGe Raised Source/Drain Poly-Si TFT 17
4.1 Introduction 17
4.2 SiGe Raised S/D Poly-Si TFT Fabrication 18
4.3 Results and Discussion 20
4.3-1 Device Characteristic of SiGe Raised Source/Drain TFTs 20
4.3-2 Dimensional Effect 21
4.3-3 Breakdown Voltage 21
4.4 Summary 22
Chapter 5 Conclusions 23
4.1 Polycrystalline Silicon Thin-Film Transistor with SiGe spacer 23
4.2 Polycrystalline Silicon Thin Film Transistor with SiGe raised Source/Drain 23

[1]A. G.. Lewis, I-W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs,” in IEDM Tech. Dig., 1990,pp. 843-846
[2]Y. Matsueda, M. Ashizawa, S. Aruga, H. Ohshima, and S. Morozumi, “New technologies for compact TFT LCDs with high-aperture ratio,” soc. Information Display, Tech. Dig., pp, 315-318, 1990.
[3]R. G.. Stewart, S. N. Lee, A. G.. Ipri, D. L. Jose, D. A. furst, S. A. Lipp, and W. R. Roach, “A 9V polysilicon LCD with integrated gray-scale drivers,” soc. Information Display, Tech. Dig.,pp. 319-322, 1990.
[4]T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano,” Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography,”IEEE Trans. Electron Devices, Vol. 42, No. 7, pp.1305-1313, 1995.
[5]S. D. S. Malhi, H. Shichijio,S. K. Banerjee, R. Sundaresan, M. Elahy, G. P. Polack, W. F. Richardaon, A. h. Shah, L. R.Hite, R. H. Womack, P. K. Chatterjee, and H. W. Lam, “Characteristics and Three-Dimenssional Integration of MOSFETs in Small-Grain LPCVD Polycrystalline Silicon,” IEEE Trans. Electric Devices, Vol.32, No.2, pp.258-281, 1985.
[6]K. YoShizaki, H.Takahashi, Y. Kamigaki, T. Yasui, K. Komori, and H. Katto, ISSCC Digest of tech. Papers, p.166, February 1985.
[7]N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I.D. French, “The Fabrication and Characteristizaion of EEPROM Arrays on Glass Using a Low-Temperature Poly-Si TFT Process,” IEEE Trans. Electron Devices, Vol. 43, No.11, pp.1930-1936, 1996.
[8]T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita, and H. Andoh, “400 dpi Integrated Contact Type Linear Image Sensors with Poly-Si TFT’s Analog Readout Circuits and Dynamics Shift Registers,” IEEE Trans. Electron Devices, Vol.38, No.5 ,pp. 1086-1039, 1991.
[9]Y. Hayashi, H. Hayashi, M. Negishi, T. Matsushita, “A Thermal Printer Head with CMOS Thin-Film Transistors and Heating Elements Integrated on a Chip,” IEEE Solid-State Circuits Conference (ISSCC), p.266, 1998.
[10]N. Yamauchi, Y. Inaba, and M. Okamura, “An Integrated Photodetector-Amplifier using a-Si p-i-n Photodiodes and Poly-Si Thin-Film Transistors,” IEEE Photonic Tech. Lett., Vol. 5, p.319, 1993.
[11]M. G.. Clark, ”Current Status and Future Prospects of Poly-Si,” IEEE proc. Circuits Devices Syst., Vol. 141, No.1, p3.3, 1994.
[12]K.Nakazawa, J. Appl. Phys., 69(3), pp.1703, 1991.
[13]K. Ono, T. Anoyama, N. Konishi, and K. Miyata, “Analysis of currnt-voltage characteristics of low-temperature-processed polysilicon thin-film transistors,” IEEE Trans. Electron. Devices, Vol. 39, no.5, p.792, 1992.
[14]M Hack, I. W. Wu, T. J. King, and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin-film transistors,” in IEEE IEDM Tech. Dig., 1993, p.385.
[15]A. Rodriguez, E. G.. Moreno, H. Pattynn, J. F. Nijis, and R. P. Mertens, “Model for the anomalous off current of polysilicon thin film transistors and diodes” IEEE Trans. Electron Devices, Vol.40, no.5, p.938, 1993.
[16]I. W. Wu, A. G. Lewis, T. Y. Huang, W. B. Jackson, and A. Chiang, ”Mechanism and device-to —device variation of leakage current in polysilicon thin film transistors,” IEEE IEDM tech. Dig., 1990, p.867.
[17]T. I. Kamins and Marcoux, “hydrogenation of transistors fabricated in polycrystalline-silicon films,” IEEE Electron Devices Lett., vol.1, no. 8, p.159, 1980.
[18]G.. P. Pollack, W. F. Richardson, S. D. S. Malhi, T. Bonifield, H. Shichijo, S.Banerjee, M. Elahy, A. h. Shah, R. Womack, and P. K. Chatterjee, “Hydrogen passivation of polysiliocn MOSFETs from a plasma nitride soure,” IEEE Electron Device Lett., vol.5, no.11, p.468, 1984.
[19]B. A. khan and R. Pandya, “Activation-energy of source-drain current in hydrogenated and unhydrogenated polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol.37, p.1727, 1990.
[20]K. Baert, H. Murai, K. Kobayashi, H. Namizaki, and M. Nunoshita, “Hydrogen passivation of polysilicon thin-film transistors by electron-cyclotron-resonance plasma,” Jpn. J. Appl. Phys., vol.32, p.2601, 1993.
[21]A. Yin and S. J. Fonash, “High-performance p-channel poly-Si TFTs using electron cyclotron resonance hydrogen plasma passivation,” IEEE Electron Device Lett., vol.15, no.12, p.502, 1994.
[22]M. Hack, A. G.. Lewis, and I. W. Wu, ”Physical models for degradation effects in polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 40, no.5, p.890, 1993.
[23]A. G. Lewis, I. W. Wu, M. Hack, A. Chiang, and R. H. Bruce, “Degradation of polysilicon TFTs during dynamic stress,” IEEE IEDM Tech. Dig., 1991, p.575.
[24]N. Kubo, N. Kusumoto, T. Inushima, S. Yamazaki, “Characteristics of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol.41, no.10, p.1876, 1994.]
[25]D. P. Gosain, J. Westwater, and S. usui, ”high performance bottom gate TFTs by excimer laser crystallization and post hydrogenation,” Jpn. J. Appl. Phys., vol.34, p.937, 1995.
[26]M.Cao, S. Tlwar, K. J. Kramer, T. W. Sigmon, and K. C. Sarawat, “A high-performance polysilicon thin-fim transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films,” IEEE Electron Devices, vol.8, p.361, 1987.
[27]M. K. Hatalis D. W. Greve, “High performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films,” IEEE Electron Device Lett., vol.8, p.361, 1987.
[28]A. Mimura, N. Konishi, K. Ono, J. Ohwada, Y. Hosokawa, Y. Ono, T. Suzuki, K. Miyata, and H. Kawakami, “High performance low-temperature poly-Si n-channel TFTs for LCD,” IEEE Electron Device Lett., vol.36, p.351, 1989.
[29]K. Tanaka, H. Arai, and S. Kohada, “Chacteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett, Vol.9, no.1, p.23, 1988.
[30]C. T. Liu and K. H. Lee, ”An experimental study on the short-channel effects in undergated polysilicon thin-film transistors with and without lightly doped drain structure,” IEEE Electron Device Lett., vol.14, no.3, p.149, 1993.
[31]J. I. Han and C. H. Han, “A self-aligned offset polysilicon thin-film transistor using photoresistor reflow,” IEEE Electron Device Lett, vol.20, no.9, p.476, 1999.
[32]J. I. Han, G. Y. Yang, and C. I. Han, “A new self-aligned offset staggered polysilicon thin-film transistor,” IEEE Electron Device Lett, vol.20, no.8, p.38, 1999.
[33]C. M. Park, B. H. Min, and M. K. Han, “Novel offset gated poly-Si TFT’s with a subgate,” IEEE Electron Device Lett, vol.46, no.7, p.1402, 1999. T. Naguchi, H. Hayashi, and T. Oshima, “Low temperature polysilicon super-thin-transistor (LSFT),’’ Jpn. J. Appl. Phys., vol.25, no.2, pp. L121,1986.
[34]T. Naguchi, H. Hayashi, and T. Oshima, “Low temperature polysilicon super-thin-transistor (LSFT),’’ Jpn. J. Appl. Phys., vol.25, no.2, pp. L121,1986.
[35]A. Kumar, J. K. O. Sin, C. T. Nguyen, and P.K.Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated-Channel Thin-Film Transistors,’’ IEEE Trans. Electron Devices, vol. 45, pp. 2514-2520, Dec. 1998.
[36]S. Zhang, C. Zhu, J. K. O. Sin, and P. K. T. Mok, “A Novel Ultrathin Elevated Channel Low-Temperature Poly-Si TFT,” IEEE Electron Device Lett., vol. 20, pp.569-571, Nov.1999.
[37]M. Miyasaka, T. Komatsu, W. Itoh, A. Yamaghchi, and H. Ohashima, “Effects of channel thickness on poly-crystalline silicon thin film transistor,’’ Ext. Abstr. SSDM, pp.647-650,1995.
[38]M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s,’’ IEEE Trans. Electron Devices, vol.37, pp. 2015-2020,Sept.1990.
[39]K. Y. Choi, K. C. Park, C. M. Park, and M. K. Han, “A new bottom-gated poly-Si thin-film transistor,” IEEE Electron Device Lett, vol.20, no.4, p.170, 1999 A. Kumar, J. K. O. Sin, C. T. Nguyen, and P.K.Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated-Channel Thin-Film Transistors,’’ IEEE Trans. Electron Devices, vol. 45, pp. 2514-2520, Dec. 1998.
[40]S. Zhang, C. Zhu, J. K. O. Sin, and P. K. T. Mok, “A Novel Ultrathin Elevated Channel Low-Temperature Poly-Si TFT,” IEEE Electron Device Lett., vol. 20, pp.569-571, Nov.1999.
[41]W-C Lee, Y-C King, T. J. King, and C. Hu, “Investigation of Poly-Si 1-x Ge x for Dual-Gate CMOS Technology,” IEEE Electron Device Lett., vol. 19, no. 7, pp. 247-249, 1998.
[42]T. J. King, J. R. Pfiester, J. D. Shott, J. P. McVittie and K. C. Saraswat. “Polycrystalline- Si 1-x Gex —Gate CMOS Technology,” IEDM Tech. Dig. 90, pp. 253-256,1990.
[43]H. C. Lin, T. G. Jung, H. Y. Lin, C. Y. Chang, T.F. Lei, P. J. wang, R. C. Deng , and J. Lin, “Deposition and Device application of in situ Boron Doped Polycrystalline SiGe Films Grown at Low Temperature,” J. Appl. Phys., Vol. 74, no.9, pp 5395-5401, 1993.
[44]B. S. Meyerson, Appl. Lett. 48, 797 (1986).
[45]JTz-Guei Jung, Chun-Yen Chang, “ Low-Temperature Epitaxial Growth of Silicon and Silicon-Germanium Alloy by Ultrahigh-Vacuum Chemical Vapor Deposition”, JJAP Vol.33 ,pp.240-246,1994
[46]T. N. Nguyen, D. L. Harame, J. M. C. Stork, F. K. LeGoues, and B. S. Meyerson, IEDM Tech. Dig., 304 (1986).

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