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研究生:徐新智
研究生(外文):Hsin-Chyh Hsu
論文名稱:提升機械模式靜電放電防護能力之元件結構設計
論文名稱(外文):Device Structure with Enhanced Machine-Model ESD Robustness in Sub-Quarter-Micron CMOS Technology
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou Ker
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:63
中文關鍵詞:靜電放電機械模式元件結構設計
外文關鍵詞:Electrostatic dischargeMachine ModelDevice structures
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摘要
在過去積體電路的靜電放電(ESD)研究中,大部分專注於改善人體模式(HBM)的靜電放電耐受能力,很少探討機械模式(MM)的靜電放電耐受能力之提升方法。然而在深次微米製程下,積體電路產品之機械模式(MM)的靜電放電耐受能力嚴重下降,已成為積體電路靜電放電防護設計的重要挑戰。因此,本論文提出有效提升機械模式靜電放電防護能力之元件結構與製程實現方法,本論文將分成三部份來探討。
本論文的第一部份,利用新型靜電放電防護佈植(ESD Implantation)技術與不同的佈局參數設計(Layout spacing)來提升閘極接地之N型金氧半場效電晶體(ggNMOS)與高低壓輸出入電路中之堆疊電晶體(stacked-NMOS) 的靜電放電防護能力,已成功地驗證於0.25微米CMOS製程中。當具有新型靜電放電防護佈植(ESD Implantation)之元件遭受靜電轟擊(Zapping)時,其可改變靜電放電電流集中在最脆弱的元件通道表面(channel surface)的缺點,迫使靜電電流流向更深與更廣的矽基板(silicon substrate),提供更大的有效區域來釋放靜電放電的電流與能量,進而提升靜電放電的耐受能力。
在本論文的第二部份,實驗結果顯示本論文所提出的設計,在相同的元件結構與尺寸下,可以將閘極接地之金氧半場效電晶體(ggNMOS)之機械模式(MM)靜電放電耐受能力有效提升50%以上,可將堆疊電晶體(stacked-NMOS)的機械模式靜電放電防護能力提升37%以上。
第三部分提出簡併低摻雜汲極(Lightly-doped drain, LDD)光罩與靜電放電防護佈植(ESD Implantation)光罩於同一道光罩,來實現在第一部份所提出的靜電放電防護之元件結構。此方法可以在不額外增加光罩的方式下,完成所提出的靜電放電防護之元件結構,並相容於具有LDD光罩的一般互補式金氧半製程。
本論文所提出的新型靜電放電防護佈植(ESD Implantation)之元件結構,已完成模擬與佈局成兩顆晶片,並在0.25微米CMOS製程中製作完成,並完成所有的元件特性及ESD特性量測。在相同的元件結構與尺寸下,其機械模式(MM)靜電放電耐受電壓可獲得大幅度的提升。
本論文之研發成果,已經提出三項美國專利申請,部份論文成果並已獲2002 IPFA Symposium國際研討會所接受,即將於七月中發表。並且,另有一篇論文投稿2002 Taiwan EMC Conference,將在十月中發表。

ABSTRACT
A novel N_ESD implantation method is proposed in this thesis to significantly improve machine-model (MM) ESD robustness of NMOS devices. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model (MM) ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a fixed device dimension of W/L=300µm/0.5µm has been successfully improved from the original 450V to become 675V in a 0.25-µm CMOS process. The MM ESD robustness of the stacked-NMOS with a fixed device dimension of W/L=300µm/0.5µm has been also successfully improved from the original 350V to become 490V in the same CMOS process. Based on this method, the ESD protection circuit with low leakage current, low junction capacitance, and higher ESD robustness can be widely used in the high-speed or mixed-voltage interface input/output (I/O) circuits.
There are three parts in the thesis. In the first part, we proposed a novel N_ESD implantation method to enhance the ESD robustness, especially the MM ESD robustness, of the ESD protection devices such as ggNMOS and stacked-NMOS in a deep sub-quarter-micron CMOS technology. The novel N_ESD implantation method has an important layout spacing parameter, which envelopes the LDD structure to prevent current crowding at the channel surface around the drain side. It can force the ESD current bypass through the large area of drain bottom plane. Therefore, the ESD protection devices with this novel N_ESD implantation have better ESD robustness, especially in the MM ESD stress. In the second part, the second breakdown current (It2) of the NMOS devices with the proposed novel N_ESD implantation method for on-chip ESD protection are measured by the transmission-line-pulse-generator (TLPG) system. The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared by ZapMaster ESD simulator, and the results are shown in Chapter 3. The MM (HBM) ESD level of the ggNMOS can be greatly improved 50% (17.4%) by using the novel N_ESD implantation method in a fixed device dimension. On the other hand, the MM ESD level of the stacked-NMOS can be greatly improved 37%.
In the third part, we propose a new process flow to fabricate the ESD protection devices with the novel N_ESD implantation proposed in Chapter 2, where the LDD mask and the N_ESD implantation mask are merged into one single mask. This new process flow is process-compatible to general CMOS process, which already has a stand-alone LDD mask. This new process flow with the novel N_ESD implantation not only reduces the fabrication cost, but also provides the integrated circuits with higher ESD robustness and faster operating speed.
Consequently, these devices with the novel N_ESD implantation have the advantages of low leakage current, low parasitic junction capacitance, and higher ESD robustness, which are more suitable for high-speed or mixed-voltage applications. The research results of this thesis have been applied 3 U.S. patents, and a conference paper has been accepted by the 2002 IPFA Symposium. Another paper is submitted to 2002 Taiwan EMC Conference.

CONTENTS
CHINESE ABSTRACT i
ENGLISH ABSTRACT iii
ACKNOWLEDGEMENTS v
CONTENTS vi
FIGURE CAPTIONS ix
CHAPTER 1 INTRODUCTION 1
1.1 Electrostatic Discharge Issue 1
1.2 On-Chip ESD Protection Design 2
1.2.1 Overview on ESD Implantation Solutions 2
1.2.2 Layout Design for ESD Protection Devices 6
1.3 Thesis Organization 7
CHAPTER 2 ESD IMPLANTATIONS AND LAYOUT DESIGN ON GGNMOS AND STACKED-NMOS FOR ON-CHIP ESD PROTECTION 9
2.1 HBM and MM ESD Current Waveforms 9
2.2 Device Structures with Novel N_ESD Implantation 10
2.2.1 GGNMOS with Novel N_ESD Implantation 10
2.2.2 Stacked-NMOS with Novel N_ESD Implantation 11
2.3 Turn-On Behavior of MOSFET’s 13
2.4 Layout Parameters Design on the ESD Protection Device 14
CHAPTER 3 EXPERIMENTAL RESULTS ON GGNMOS AND STACKED-NMOS WITH NOVEL N_ESD IMPLAN- TATION 17
3.1 ESD Testing of CMOS IC’s 17
3.1.1 The Test Chips 17
3.1.2 DC I-V Characteristics 17
3.1.3 It2 and ESD Level 17
3.2 Experimental Results of GGNMOS with Novel N_ESD Implantation 18
3.2.1 DC I-V Characteristics of GGNMOS 18
3.2.2 TLPG Measurement Results of GGNMOS 19
3.2.3 ZapMaster Measurement Results of GGNMOS 20
3.3 Experimental Results of Stacked-NMOS with Novel N_ESD Implantation 21
3.3.1 DC I-V Characteristics of Stacked-NMOS 21
3.3.2 TLPG Measurement Results of Stacked-NMOS 22
3.3.3 ZapMaster Measurement Results of Stacked-NMOS 23
CHAPTER 4 NEW FABRICATION PROCESS TO IMPLEMENT THE NMOS WITH NOVEL N_ESD IMPLANTA- TION 26
4.1 The Concept of the New Process Method 26
4.2 The Fabrication Process of the N_ESD Implantation 26
4.3 The Advantages of the New Process Method 27
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 29
5.1. Conclusions 29
5.2. Future Works 30
REFERENCES 31
FIGURES 34
VITA 63

REFERENCES
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[29] J. Barth, K. Verhaege, L. Henry, and J. Richner, “TLP calibration, correlation, standards, and new techniques,” in Proc. of EOS/ESD Symp., 2000, pp. 85-96.
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