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臺灣博碩士論文加值系統

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研究生:陳冠勳
研究生(外文):Guan-Xun Chen
論文名稱:數位類比轉換器之內建測試電路研究
論文名稱(外文):A New BIST Scheme for Digital-to-Analog Converters
指導教授:李崇仁李崇仁引用關係
指導教授(外文):Chung-Len Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:34
中文關鍵詞:類比加法器製程容忍度
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由於超大型積體電路技術的快速進步,測試類比混合電路變得越來越困難。在這篇論文中,我們採用類比加法器把電壓量測轉換到時間量測來完成對數位類比轉換器所提出的內建測試方法。為了保證測試的精準度,在電路中會加上測試電路來針對製程容忍度所產生的誤差來作校正。此方法在八位元數位類比轉換器當待測電路下得到驗證。

Testing analog/mixed-signal circuitry becomes more and more difficult due to the rapid advance of the VLSI technology. In this thesis, we propose a new BIST scheme for testing Digital-to-Analog Converters (DACs) by adopting an analog summer to transform the voltage measurement into the timing measurement. To guarantee the accuracy of testing, calibration circuits are added to calibrate errors on the testing circuit caused by process tolerance. The scheme has been demonstrated by using an 8-bit DAC under test.

Contents
Chinese Abstract
English Abstract
Acknowledgement
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Motivation and Review
1.2 Review on Characteristics of a DAC
1.3 Thesis Outline
Chapter 2 The Proposed DAC BIST Circuit
2.1 Idea
2.2 BIST Circuit
2.3 Detailed Sub-Circuits
2.3.1 Charge Pump
2.3.2 CMOS Schmitt Trigger
2.4 Analog Summer
Chapter 3 Calibration Circuit
3.1 Error Sources
3.2 Calibration of Errors
3.2.1 Digital-Controlled Charge Pump (DCCP)
3.2.2 Digital-Controlled Schmitt Trigger (DCST)
3.2.3 Algorithm of the ALU
Chapter 4 Simulation Results
4.1 Simulation Results of the BIST Circuit without Calibration
4.2 Simulation Results of the BIST Circuit with Calibration
4.3 Performance of the BIST Circuit
4.3.1 Ideal Timing Measurement
4.3.2 Offset Error
4.3.3 Gain Error
4.3.4 DNL Error
4.3.5 INL Error
4.3.6 Maximum Resolution of BIST Circuit
4.4 Calibration Result
4.4.1 Characteristic of Digital-Controlled Charge Pump (DCCP)
4.4.2 Characteristic of Digital-Controlled Schmitt Trigger (DCST)
4.4.3 An Illustration for Calibration
4.5 The Worst Case Simulation
4.6 Summary
Chapter 5 Conclusion
Reference

[1] Jeng-Horng Tsai, Ming-Jun Hsiao and Tsin-Yuan Chang, “An Embedded Built-In Self-Test Approach for Digital-to-Analog Converters”, Asian Test Symposium, pp.423-428, 2001.
[2] K. Arabi, B. Kaminska, and J. Rzeszut, “BIST for D/A and A/D Converters”, IEEE Design and Test of Computers, pp.40-49, 1996.
[3] K. Arabi, B. Kaminska, and J. Rzeszut, “A New Built-In Self-Test Approach for Digital-to-Analog and Analog-to-Digital Converters”, ICCAD, pp.491-494, 1994.
[4] K. Arabi, B. Kaminska, and J. Rzeszut, “A Built-In Self-Test Approach for Medium to High Resolution Digital-to-Analog Converters”, Third Asia Test Symposium, pp.373-378, 1994.
[5] Yun-Che Wen and Kuen-Jong Lee. “BIST Structure for DAC Testing”, Electronics Letters, 34(12):1173-1174, 1998.
[6] Jiun-Lang Huang, Chee-Kian Ong, and Kwang-Ting Cheng, “A BIST Scheme for On-Chip ADC and DAC Testing”, Design, Automation and Test in Europe Conference and Exhibition 2000, pp.216-220, 2000.
[7] D. Johns and K. Martin, “Analog Integrated Circuit Design, chapter 11.5”, pp. 454-459, John Wiley & Sons, Inc., New York, first edition, 1996.
[8] Zhenhua Wang, “CMOS Adjustable schmitt Triggers”, IEEE Transactions on Instrumentation and Measurement, pp.601-605, 1991.
[9] Daejeong Kim, Joongsik Kih, and Wonchan Kim, “A New Waveform-Reshaping Circuit: An Alternative Approach to schmitt Trigger”, IEEE Journal of Solid-State Circuits, pp. 162-164, 1993.
[10] Cheuk-Him To, Cheong-Fat Chan, and Oliver Chiu-Sing Choy, “A Simple CMOS Digital Controlled Oscillator with High Resolution and Linearity”, Circuit and System, 1998, ISCAS ’98. Proceedings of the 1998 IEEE International Symposium on, vol. 2, pp. 371-373, 1998.
[11] S. Bernard, F. Azais, Y. Bertrand and M. Renovell, “A High Accuracy Triangle-Wave Signal Generator for On-Chip ADC Testing”, 7th IEEE European Test Workshop, pp. 365-370, 2002.

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