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研究生:楊景翔
研究生(外文):Ching Hsiang Yang
論文名稱:鎖相迴路障礙診斷之可測試性電路設計
論文名稱(外文):A DFT Scheme for PLL Fault Diagnosis
指導教授:李崇仁李崇仁引用關係
指導教授(外文):Chung Len Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:39
中文關鍵詞:鎖相迴路診斷可測試性電路設計
外文關鍵詞:PLLDiagnosisDFT
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本論文是針對鎖相迴做障礙診斷的可測試性電路設計。在現今的通訊領域當中,鎖相迴路扮演相當重要的角色,像是低抖動的頻率合成器、時脈回復和同步作用;當鎖相迴路中有障礙存在時,所提供的頻率和效能將會與規格不符。因此,在量產測試不符合規格時,若能診斷出錯誤的部分,將能夠縮短除錯時間、縮小除錯範圍,進而提升良率、降低生產成本。
本文中,我們提出了一個診斷鎖相迴路可測試性電路設計的方法,在鎖相迴路當中增加了兩個測試時脈和隨測試時脈而變動的一些測試電路,診斷出在鎖相迴路當中一些具代表性的障礙,並對壓控震盪器的障礙作分析。最後我們用tsmc 0.35 CMOS製成完成全部得電路並證明這個診斷方法的可行性。

This thesis proposes a DFT scheme for phase-locked loop diagnosis. PLL plays a very import role in communication systems nowadays, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield and achieve cost reduction, it is important to diagnose it to identify the faulty part when it does not meet the specifications as expected.
In the thesis, a DFT scheme for PLL diagnosis is presented. Two test clocks and design-for-test(DFT) circuits controlled by test clocks are applied. The proposed method identifies some representative faults and analyzes faults in VCO. Ultimately, we completed the whole circuit with 0.35-μm N-well technology as an example to demonstrate the feasibility.

Contents
Chinese Abstract ...…...……………………...……………………………………… i
English Abstract ……………………………………..……………………………… ii
Acknowledgment ..…..……………………………….……………………………… iii
Contents ...………………………………………………..………………………….. iv
List of Figures ……………………………………………..………………………… vi
List of Tables ...………………………………………………..…………………….. viii
Chapter 1 Introduction
1.1 Motivation…………………………………………………………….…..1
1.2 Previous Work………………………………………………………….…2
1.3 Outline of Thesis………………………………………………………….3
Chapter 2 A Diagnosis Technique for Phase Locked Loop
2.1 Fault Models and Fault Analysis…………………………………..…..… 4
2.1.1 Hard Fault………………………………………………..……..…4
2.1.2 Soft Fault………………………………………………..………...5
2.2 Diagnosis method for PLL………………………………………..…….…6
2.2.1 Some Representative Hard Faults……………….……………...…6
2.2.2 DFT Circuits in the Diagnosis Scheme…………….…….……..…9
2.2.3 Soft Faults in Charge Pump and Loop Filter………………….….13
2.2.4 Hard Faults and Soft Faults in VCO……………..….……………16
2.3 Summary……………………………………………….………………....26
Chapter 3 Simulation Results
3.1 Post-Simulation Results………………………………….…………….…27
3.2 Layout Consideration………………...……………….………………….31
Chapter 4 Conclusion…………………………………………………….…………33
Appendix………………………………………………………………………….……34
Reference…………………………………………………………………..…………..37
Vita………………………………………………………………………….………….39

1. John Wiley & Sons, Frequency Synthesis by Phase Lock., Inc, second ed., 2000.
2. Roland E. Best, Phase-Locked Loops, Design, Simulation and Applications. McGraw-Hill, Third Edition.
3. P. V. Brennan, Phase-Locked Loops: Principles and Practice, MacMillan Press Ltd., Great Britain, 1996.
4. C. Dislis, J. H. Dick, et al, “Test Economics and Design for Testability for Electronic Circuits and System,” Ellis Horwood, 1995.
5. Z. You, E. Sanchez-Sinencio, and J. P. de Gyvez, “ Analog System-level Fault Diagnosis Based on a Symbolic Method in the Frequency Domain,” IEEE Trans. Instrum. Meas., vol. 44, pp. 28-35, Feb. 1995.
6. L. Rapisarda, and R. A. Decarlo, “ Analog Multi-frequency Fault Diagnosis,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 223-233, April 1983.
7. Seongwon Kim; Soma, M. “An All-digital Built-in Self-test for High-speed Phase-locked Loops ” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 48 Issue: 2 , Feb. 2001
8. P. Goteti, G. Devarayanadurg, M. Soma, ”DFT for Embedded Charge-Pump PLL Systems Incorporating IEEE 1149.1”, Custom Integrated Circuits Conf., pp.10.3.1-10.3.4, 1997.
9. S. Sunter, A. Roy, ”BIST for Phase-Locked Loops in Digital Applications”, Proceedings IEEE ITC, pp. 532-540, 1999.
10. Martin John Burbidge, Frederic Poullet, “ Investigations for Minium Invansion Digital Only Built-in Ramp Based Test Techniques For Charge Pump PLL’s ”
7th IEEE European Test Workshop,pp 371-377,2002
11. Ozev, S.; Orailoglu, A. “System-level Test Synthesis for Mixed-signal Designs ” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 48 Issue: 6 , June 2001
12. Chung Kin Ho; Shepherd, P.R.; Eberhardt, F.; Tenten, W “Hierarchical Fault Diagnosis of Analog Integrated Circuits ” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , Volume: 48 Issue:8, Aug. 2001
13. Rizk, M.R.M.; Yacout, M.Y “Fault Diagnosis of Mixed Digital and Linear Analog Circuits ” Radio Science Conference, 2001. NRSC 2001. Proceedings of the Eighteenth National , Volume: 2 , 2001
14. J.W.Lin, C.L.Lee and J.E.Chen, "A Design for Diagnosis Scheme for the PLL", IEEE IMSTW, pp.5-8, 2001; "An Efficient Test and Diagnosis Scheme for The Feedback Type of Analog Circuits with Minimal Added Circuits", IEEE Design, Automation and Test in Europe, pp., 2002

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