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研究生:李志虹
研究生(外文):Chih-Hun Lee
論文名稱:深次微米CMOS技術應用於2.4GHz無線區域網路前端接收器之影響
論文名稱(外文):The Impact of Deep-Submicron CMOS Technology on 2.4-GHz Wireless LAN Receiver Front-End
指導教授:溫瓌岸桂正楣
指導教授(外文):Kuei-Ann WenZhung-Mei Gui
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:100
中文關鍵詞:802.11b低雜訊放大器次諧波混頻器直流帶斥濾波器
外文關鍵詞:802.11bLNASub-harmonic MixerDC-offsets cancellation
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本設計規格依循一2.4GHz, 65mW, 0.25um的單晶片CMOS射頻前端接收器,其符合無線區域網路802.11b標準協定。 在此之前, CMOS射頻晶片中重要的元件, 如CMOS電晶體, 平面電感, 金屬絕緣式或電晶體式電容, 晶片封裝接腳等, 已預先精確地模組化, 並且作一最佳化考量。 論文首先敘述無線區域網路802.11b系統規劃。 接收器採用直接降頻架構, 減少了外接被動元件的需求, 例如濾除鏡像濾波器。 接收器使用2.5伏偏壓, 包含一個低功率雙增益模式的低雜訊放大器, 在後續兩路互相正交的訊號路徑, 各有一電流注入式的次諧波混頻器, 及具雙端中頻輸出放大器的直流帶斥濾波器。 接下來, 前端接收器的中頻輸出接至可調式增益放大器與5階柴比雪夫低通濾波器, 最後是類比數位轉換器。 前端接收器的模擬結果, 在高增益模式下, 輸入 IP3為 —30.1 dBm, P1dB為 —38 dBm, 在低增益模式下, 輸入 IP3 為 2.1 dBm, P1dB 為 —5 dBm。

A monolithic 2.4-GHz, 65-mW, 0.25-um CMOS receiver front-end which meets the specifications of the Wireless Local Area Network (WLAN) 802.11b standard is described. In advance, significant CMOS RF-IC’s devices, which include MOS transistors, planar inductors, MIM/MOSFET capacitors, and IC package bondwires, have been accurately modeled and optimized. A description is given for the planning of a WLAN 802.11b system with direct-conversion architecture, which eliminates the need for external discrete components, such as image-reject filter. The prototype receiver utilizes a 2.5-V supply voltage and includes a current-reuse dual-gain low noise amplifier and two quadrature signal paths, each of which is composed of a current-injection sub-harmonic mixer, and a DC notch filter with different outputs of an IF amplifier. Subsequently, the IF outputs of the receiver front-end are connected to a variable-gain amplifier and a 5-th order Chebyshev low pass filter (LPF) followed by an analog-to-digital converter (ADC). The experimental receiver front-end has a simulated input referred IP3 of —30.1 dBm (at high gain mode) or 2.1 dBm (at low gain mode), a P1dB of —38 dBm (at high gain mode) or -5 dBm (at low gain mode). Both on-wafer and packaged implementations will be presented for design analysis and verifications.

Contents
摘要
Abstract
自序
Contents
List of Figures
List of Tables
Chapter1. Introduction
1.1 Motivation
1.2 Thesis Organization
Chapter2. Device Physics and Characteristics
2.1 MOS Transistors
2.1.1 Carrier Velocity Saturation
2.1.2 Mobility Degradations with Vertical Field
2.1.3 Noise in MOSFET
2.1.3.1 High Frequency Noise
2.1.3.2 Flicker Noise
2.1.3.2.1 Modeling of 1/f Noise
2.1.3.2.2 1/f Noise Optimization Techniques
2.1.3.3 MOSFET Noise Model
2.2 Inductors
2.2.1 Monolithic Inductors
2.2.2 Bondwire Inductors
2.3 Capacitors
2.3.1 MIM Capacitors
2.3.2 MOSFET Capacitors
2.4 RLC Network
2.5 Conclusions
Chapter3. RF Receiver Considerations
3.1 Receiver Types
3.1.1 Heterodyne Receivers
3.1.1.1 Image-Rejection Receivers
3.1.1.2 Double-Conversion Receivers
3.1.2 Homodyne Receivers
3.2 WLAN 802.11b Transceiver Architecture
3.2.1 Standards of the IEEE 802.11b
3.2.2 WLAN 802.11b Receiver Specifications
3.2.3 WLAN 802.11b Circuits Specifications
Chapter4. Low Noise Amplifier (LNA) Design
4.1 LNA Prototype Configuration
4.2 Input Impedance Matching
4.3 Gain Analysis
4.4 Noise Analysis
4.5 Dynamic Range
4.6 Implementation: A Low-Power LNA with Dual-Gain Mechanism
4.7 Conclusions
Chapter5. Down-Conversion Sub-Harmonic Mixer Design
5.1 Sub-Harmonic Mixer Structure
5.2 Gain Analysis
5.3 Noise Analysis
5.4 Linearity Consideration
5.5 Implementation: A Current-Injection Sub-Harmonic Mixer
5.6 Conclusions
Chapter6. RF Receiver Front-End Implementation
6.1 A 2.4GHz Direct-Conversion Sub-harmonic Receiver Front-End
6.2 DC-Offset Cancellation
6.3 Constant-Gm Bias Circuit
6.4 Quadrature Generator
6.5 Layouts of Chip and PCB
6.6 Simulation Results
6.7 System Verifications
6.8 Conclusions
Chapter7. Conclusions and Future Work
7.1 Measurement and Conclusions
7.2 Future Work
Appendix I. Flicker Noise Measurement and Modeling
References
作者簡介

References
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