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研究生:陳銀康
研究生(外文):Tang Ning Kang
論文名稱:互補式金氧半導體影像感測器技術(II)-一個10位元連續逼近類比數位轉換器及系統偏壓電路
論文名稱(外文):CMOS Image Sensor Technology(II)-A 10-bit Successive Approximation Analog-To-Digital Converter and System Biasing Circuit
指導教授:吳慶源
指導教授(外文):Ching-Yuan Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:63
中文關鍵詞:影像感測器
外文關鍵詞:CMOS Image Sensor
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近來,互補式金氧半導體影像感測器已經受到廣泛的注意,顧客對於微型化、低功率、低成本的需求成為其受到持續關注的主要原因。互補式金氧半導體影像感測器提供了整合超大型積體電路中各個系統在同一個晶片上的機會,並且減少了電路版上離散的電路元件數量,降低包裝成本。一個包含時序控制器,感測器陣列,訊號處理器,類比到數位轉換器,數位介面的單晶片照相機是可預期的。類比到數位轉換器的解析度及轉換速率對圖像品質有很大的影響,尤其是在錄影的應用。感測器的類比部份需要和PVT效應無關的偏壓電路以獲得穩定性及雜訊的壓抑。
本論文中報告10位元連續逼近類比數位轉換器及系統偏壓電路。所設計的電路以SPICE及台積電1P/5M 0.25微米 3.3V 的spice 模型模擬。

Recently, there has been a growing interest in CMOS image sensors. The major reason for this interest is the customer demand for miniaturized, low-power, and low-coast digital cameras. CMOS image sensors offer a great potential to integrate a significant amount of VLSI electronics on a single chip and reduce discrete components and packaging costs. It is now straightforward to envision a single-chip camera that has integrated timing and control electronics, sensor array, signal processing electronics, analog-to-digital converter (ADC) and full digital interface. The resolution and conversion rate of the ADC has much influence on the image quality especially for video application. The analog portions in the sensors require a system biasing circuit that frees from PVT effect to obtain stability and noise suppression.
A 10-bit successive approximation ADC and the system biasing circuit are presented in this thesis. The designed circuits are simulated in SPICE and TSMC 1P/5M 0.25um 3.3V spice model.

Contents
Abstract
Acknowledgement
Contents
Figure Captions
Table Captions
Chapter 1 Introduction
Chapter 2 A 10-bit Fully Differential Successive Approximatoin ADC
2.1 ADC Architecture
2.2 Capacitive Maindac and Resistive Subdac
2.3 Successive Approximation Register (SAR) and Control Logic
2.4 Comparator and Latch
2.5 Simulation Result
Chapter 3 System Biasing Circuit
3.1 Main Reference Voltage Generator
3.2 Global Biasing Current Source
3.3 Voltage Regulator
3.4 ADC Reference Voltage Buffer
3.5 Simulation Result
Chapter 4 Conclusion
Figure Captions
Figure 2.1 ADC schematic diagram
Figure 2.2 Timing of ADC
Figure 2.3 Input signal timing during tracking phase
Figure 2.4 VCLGEN circuit
Figure 2.5 Two capacitor arrays and the control signal diagram
Figure 2.6 SWCAP schematic diagram
Figure 2.7 SWCAP symbol diagram
Figure 2.8 SWCAPVR schematic diagram
Figure 2.9 SWCAPVR symbol diagram
Figure 2.10 Pass-transistor used in the resistive Subdac
Figure 2.11 Resistor ladder and control signal diagram(a)
Figure 2.12 Resistor ladder and its control signal diagram(b)
Figure 2.13 SR D-FF Q<0>
Figure 2.14 SR D-FF Q<i>
Figure 2.15 SAR D-FF S<0>
Figure 2.16 SAR D-FF S<i>
Figure 2.17 CapArrayin for input is S<i> where i<4
Figure 2.18 Multiplexer at one of the output of the 3-2 decoder
Figure 2.19 OUTVALID generator
Figure 2.20 Comparator stages
Figure 2.21 Latch circuit
Figure 2.22 Biasing circuit of the comparator and latch
Figure 2.23 Ideal ADC transfer curve
Figure 2.24 Input and output voltage of the comparator
Figure 2.25 Conversion bits for 0LSB~4LSB
Figure 2.26 Conversion bits of 343LSB~339LSB
Figure 2.27 Conversion bits of 681LSB~685LSB
Figure 2.28 Conversion bits of 1024LSB~1020LSB
Figure 2.29 SWCMP generator
Figure 3.1 The main reference voltage generator
Figure 3.2 Operational Amplifier OP1
Figure 3.3 OP1 biasing circuit
Figure 3.4 Global biasing current source
Figure 3.4 OP2/OP5 include the biasing circuit
Figure 3.5 The voltage regulator
Figure 3.6 The circuit of OP3 and OP4
Figure 3.7 The ADC reference voltage buffer
Figure 3.8 The biasing circuit of the ADC reference voltage buffer
Figure 3.9 Transient response of the main reference voltage generator
Figure 3.10 and dependence on
Figure 3.10 and dependence on
Figure 3.12 dependence on PVT effect
Figure 3.13 The current source PCS dependence on PVT effect
Table Captions
Table 2.1 Truth Table of SAR D-FF S<0>
Table 2.2 Truth table of SAR D-FF S<i>
Table 2.3 Device dimension of the comparator
Table 2.4 Device dimension of the latch
Table 2.5 Conversion bits of the critical input signal
Table 2.5 ADC key features
Table 3.1 Device size and RC values of the main reference voltage generator
Table 3.2 Device size in the global biasing current source
Table 3.3 Device size of OP2, OP5 and its biasing circuit
Table 3.4 Device size of OP3 and OP4
Table 3.5 Device size of the ADC reference voltage buffer
Table 3.6 The threshold voltage of MOS transistor under different process corner

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