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研究生:黃自立
研究生(外文):Lily Huang
論文名稱:電晶體層級電路描述之邏輯粹取
論文名稱(外文):Logic Extraction from Transistor Level Circuit Netlists
指導教授:周景揚周景揚引用關係
指導教授(外文):Jing-Yang Jou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:45
中文關鍵詞:邏輯粹取電路描述
外文關鍵詞:Logic Extractionnetlist
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在電腦輔助電路設計的領域中,如何在一個大型電路中尋找某附屬電路的問題是被廣泛研究的。現今這些問題都是以圖形辨識的方法解決,但這些方法都沒有利用到任何電路的特性,也很有可能會在圖形的轉換過程中喪失了電路的拓撲結構(topological structure),而導致無法辨識出某些特定的電路,像是輸入點短路的邏輯閘。如果整個電路都需要以較高階的模組表示,這些方法更需要多次的執行才能粹取出每一種邏輯電路。我們利用通道圖分割(channel graph partition)以及電路編碼理論(circuit encoding algorithm),提出了一種邏輯粹取的方法,只要處理過一次電路,不需任何的前置作業,就可以把整個電路描述由電晶體層級提升到邏輯層級。以標準元件庫(standard cell library)中的基本邏輯閘為範本電路(pattern circuit)的來源,以及離線處理已知的範本電路辨識資訊,更加提升了整個方法的效能及可再利用性。包含組合電路以及循序電路的實驗結果可以證明這個方法在執行時間以及記憶體需求上都與電路大小有近似線性的關係。

The problem of finding subcircuits in a larger circuit arises in many contexts in computer-aided design. This is a problem currently solved by using various heuristics purely based on graph isomorphism. Such techniques, however, cannot utilize any circuit properties and usually lost the topological circuit structure, which led to failure in some cases such as shorting-input circuits. If the whole circuit needs to be represented in higher level models, it even takes numerous runs to extract every kind of subcircuits by these techniques. We present a logic extraction approach based on channel graph partition and modified circuit encoding algorithm. Without any pre-processing, it needs to traverse the input circuit only once, and converts the entire circuit netlist from transistor level to gate level. The reusability and efficiency are further achieved by using the elemental logic gates in standard cell library as the source of pattern circuits, and preparing the priori known pattern circuit information for identification off-line. The experiments on several real circuits containing sequential and combination logics show the near-linear performance in run time and memory usage.

Contents
摘要 i
ABSTRACT ii
ACKNOWLEDGEMENT iii
CONTENTS iv
LIST OF TABLES vi
LIST OF FIGURES vii
Chapter 1 Introduction 1
Chapter 2 Preliminaries 5
2.1 Spice Netlist Format 5
2.2 Graph Representation 6
2.3 Related Works 8
2.3.1 SubGemini 8
2.3.2 Resource Management 11
2.3.3 DECIDE 12
2.3.4 Summary 14
2.4 Research Problem 14
Chapter 3 Proposed Approach 17
3.1 DCC Partition Method 17
3.2 Circuit-Encoding Algorithm 22
3.3 DCC Level Logic Extraction 29
3.3.1 PCL Setup 29
3.3.2 Logic Extraction from Input Circuit 31
3.3.3 Flip-flop Extraction 34
Chapter 4 Experiment and Verification 37
4.1 Experimental Result and Analysis 37
4.2 Verification 43
Chapter 5 Conclusions and Future Work 45
Reference i

[1] Kai-Ti Huang and David Overhauser, “A Novel Algorithm for Circuit Recognition”, 1995 IEEE International symposium on, Circuit and Systems, Volume 3, pp. 1695-1698, May 1994.
[2] C. Ebeling , “GeminiII: A Second Generation Layout Validation Tool”, Proceedings of the Conference on Computer Aided Design (ICCAD), pp.610-615, Nov 1988.
[3] C. Ebeling and O. Zajicek, “Validating VLSI Circuit Layout by Wirelist Comparison”, Proceedings of the Conference on Computer Aided Design (ICCAD), pp. 172-173, 1993.
[4] M. Ohlrich, C. Ebeling, E. Ginting, and L. Sather, “SubGemini: Identifying Subcircuits Using a Fast Subgraph Isomorphism Algorithm”, Proceedings of Design Automation Conference, pp. 31-37, June 1993.
[5] Z. Ling and D. Y. Y. Yun, “An Efficient Subcircuit Extraction Algorithm by Resource Management”, 2nd International Conference on ASIC, pp. 9-14, Oct 1996.
[6] N. P. Keng and D. Y. Y. Yun, “A Planning /Scheduling Methodology for the Constrained Resource Problem”, Proceedings 1989 International Joint Conference on Artificial Intelligence, pp. 20-25, Aug 1989.
[7] Wei-Hsin Chang, Shuenn-Der Tzeng, and Chen-Yi Lee, “A Novel Subcircuit Extraction Algorithm by Recursive Identification Scheme”, 2001 IEEE International Symposium on Circuits and Systems, Volume: 5 , pp. 491 -494, 2001.
[8] D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level DC-Connected Components in Logic Simulation”, Proceedings of Design Automation Conference, June 1993.
[9] Bruno T. Messmer and Horst Bunke, “Efficient Subgraph Isomorphism Detection: a Decomposition Approach”, IEEE Transactions on Knowledge and Data Engineering, Volume 12, No. 2, Mar/Apr 2000.

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