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研究生:林季穎
論文名稱:MPEG-4以內容為基礎的算術編碼之分析設計與軟硬體共同驗證
論文名稱(外文):Design, analysis and hardware-software co-verification of MPEG-4 context-based arithmetic encoding
指導教授:任健葳
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:MPEG-4以內容為基礎的算術編碼
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  • 被引用被引用:0
  • 點閱點閱:149
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本篇論文對二元形狀方格(Binary Alpha Block, BAB)與以內容為基礎的算數編碼(Context based Arithmetic Coding, CAE)做詳盡的統計分析,並基於這些統計分析,提出了一個有效的BAB編碼傳輸方式與一個CAE單元的架構,來提高MPEG-4形狀編碼整體的效能。本篇論文實現了一個記憶體控制單元與一個CAE單元,並在ARM的發展環境中與整個MPEG-4形狀編碼的程式做軟硬體的共同驗證。
在過去研究中,CAE單元的效能最佳化,常常受限於其必須連續處理的特性,而無法有較佳的效能改進。在本篇論文中,CAE的統計方面顯示,內容(context)全為0或是1的符號(symbol)大多成群的出現;而針對此特性,我們設計了一個採用預測性處理的CAE硬體來做效能的最佳化。此加速硬體能在一個時脈週期(clock cycle)處理兩個內容全是0或是1的符號,進而減少整個CAE的運算時脈週期(operation clock cycles);跟傳統的架構做比較,本篇論文提出的架構可以加速1.45倍。基於BAB的圖案特性,模擬結果顯示,將數條連續一樣的BAB線(row)編碼成一次BAB線的資料傳輸,可將邊緣BAB(Boundary BAB)的資料傳送次數減少到33.52%左右;當這樣的編碼應用到所有的BAB的資料傳送時,則可將整個傳送次數減少到8%左右。
在CAE 硬體單元的驗證上,此硬體單元在ARM的發展環境中與整個MPEG-4形狀編碼的程式做軟硬體的共同驗證。為了縮短整個系統發展時間與達到有效的軟硬體共同驗證,我們也提出了一個系統設計流程。此系統設計流程採用了適用於軟硬體共同驗證的應用程式介面(Application Program Interface, API)與部分的軟硬體共同驗證(Semi-HW/SW Co-verification)。

CHAPTER 1 INTRODUCTION
CHAPTER 2 STATISTICS AND ANALYSIS
CHAPTER 3 ARCHITECTURE DESIGN
CHAPTER 4 HARDWARE-SOFTWARE CO-VERIFICATION
CHAPTER 5 CONCLUSION AND FUTURE WORK
REFERENCE
APPENDIX

Reference
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