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研究生:林昭斌
研究生(外文):Chaobin Lin
論文名稱:限定輸出誤差之乘法器自動合成
論文名稱(外文):On Multiplier Synthesis under Error Constraint
指導教授:周景揚周景揚引用關係
指導教授(外文):Jing-Yang Jou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:53
中文關鍵詞:乘法乘法器
外文關鍵詞:multiplicationmultiplier
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  • 點閱點閱:176
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  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
在各種處理器中,乘法器的速度往往是決定效能的關鍵。再者,由於在各種電路中廣泛的使用乘法器,因此如何自動化的產生需要的乘法器,成為電路設計自動化的重要課題。在本篇論文中,我們提出了由誤差大小來決定硬體的自動乘法產生器。藉著容許些許的誤差,我們可以用更小的面積來實現更快速的乘法器。考慮到信號到達時間的曲線圖,我們也為以時間為考量的繞線和電路配置(placement)提出一些技巧,來做時序最佳化。在乘法產生器的流程中,藉由整合電路合成、配置以及再合成的步驟,我們將可得到優於其他傳統作法產生的乘法器。

The thesis presents an automatic error-controlled hardware-configurable multiplier generator. The determination of the hardware of a multiplier is based on the error constraint given by users. With allowing some rounding errors, a significant reduction in area and delay can be achieved. By considering signal arrival profile, we also proposed several techniques for timing driven routing and placement to optimize the timing. By integrating synthesis, placement and resynthesis processes in the multiplier generation flow, the multipliers generated by our multiplier generator outperform other schemes used for comparison as shown in our experimental results.

摘要 i
ABSTRACT ii
Acknowledgements iii
Contents iv
List of Figures v
List of Tables vii
1. Introduction 1
2. Truncated Multiplication 5
2.1. Truncated Multiplication with Constant Correction 6
2.2. Truncated Multiplication with Variable Correction 7
3. Multiplier Generation Flow 9
3.1. Timing Model 10
3.2. Partial Production Generation 13
3.3. Placement & Buffer Insertion 19
3.4. Column Compress Tree (CCT) Connectivity Generation 23
3.5. Rewiring for Timing Improvement 27
3.5.1. Minimax Problem 29
3.5.2. Rewiring Algorithm 30
3.6. Final Adder 33
4. Experimental Result 38
5. Conclusions 44
References 45

[1] Ya-Chi Yang and Jing-Yang Jou, “On Layout-Driven Automatic Multiplier Generation,” Master Thesis, National Chiao Tung University, June 2001.
[2] Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Second edition, Addison-Wesley.
[3] K. Hwang, Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[4] Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, and Yasutaka Horiba, “A 600-MHz 54 54-bit Multiplier with Rectangular-Styled Wallace Tree,” IEEE J.Solid-State Circuits, vol. 36, pp. 249-257, Feb. 2001.
[5] A. Weinberger, “4:2 Carry-Save Adder Module”, IBM Technical Disclosure Bull., vol 23, Jan. 1981.
[6] S. F. Oberman and M. J. Flynn, “Design Issues in Division and Other Floating-Point Operations," IEEE Transactions on Computers, 1997.
[7] Hesham Abdulaziz Al-Twaijry, “Area and Performance Optimized CMOS Multipliers,” PhD Thesis, Stanford University, August 1997.
[8] A. D. Booth, “A Signed Binary Multiplication Technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236-240, 1951.
[9] V. G. Oklobdzija and S. S. Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transactions on Computers, vol.45, no.3, March 1996.
[10] Lan-Da Van, Shuenn-Shyang Wang, and Wu-Shiung Feng, “Design of the Lower Error Fixed-Width Multiplier and its Application,” IEEE Transactions on Circuit and Systems, vol. 47, no. 10, October 2000.
[11] Jer Min Jou, Shiann Rong Kuang, and Ren Der Chen, “Design of Low-Error Fixed-Width Multipliers for DSP Applications,” IEEE Transactions on Circuit and System, vol. 46, no. 6, June 1999.
[12] P. F. Stelling, C. U. Martel, V. G. Oklobzija, and R. Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Transaction on Computers, vol. 47, no .3, Mar 1998.
[13] Earl E. Swartzlander, Jr, ”Truncated Multiplication with Approximate Rounding,” 1999. Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1480-1483, 1999.
[14] M. J. Schulte and E. E. Swartzlander, Jr., “Truncated Multiplication with Correction Constant," in VLSI Signal Processing, VI, pp. 388-396, 1993.
[15] Schulte, M.J., Stine, J.E., and Jansen, J.G., “Reduced Power Dissipation Through Truncated Multiplication,” in Proceedings of. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp. 61-69, 1999.
[16] E. J. King and E. E. Swartzlander, Jr., “Data-dependent Truncated Scheme for Parallel Multiplication," in Proceedings of the Thirty First Asilomar Conference on Signals, Circuits and Systems, pp. 1178-1182, 1998.

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