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研究生:蔡淑惠
研究生(外文):Shu-Hui Tsai
論文名稱:最小轉換差動信號傳送器
論文名稱(外文):Transition-Minimized Differential Signaling (TMDS) Transmitter
指導教授:吳錦川
指導教授(外文):Jiin-Chuan Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:67
中文關鍵詞:最小轉換差動信號傳送器鎖相迴路
外文關鍵詞:Transition Minimized Differential SignalingTransmitterPhase Locked Loop
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本篇論文是設計一個應用於高速串列數位影像傳輸介面,使用最小轉換差動信號的傳送器。整個傳送器電路包含多相位之鎖相迴路,十對一多工器和輸出驅動器。
多相位之鎖相迴路的輸入頻率為25∼165MHz,提供10個相位且輸出頻率同樣為25∼165MHz的時脈,所包含的電路有相位∕頻率偵測器、充電泵浦、迴路濾波器、十個相位的壓控振盪器。多相位鎖相迴路可應用於解析度由VGA(640×480)到UXGA(1600×1200)平面顯示器的傳輸介面,使用5級差動式多相位壓控振盪器產生10個相位精確且平均分布於一個週期內的時脈,提供十對一多工器將一組並列資料轉換成串列輸出。最後再透過一輸出驅動器,增加電流驅動能力,完成整個傳送器的設計。
此傳送器採用 1P4M CMOS製程技術實現,電壓電源為3.3V。當輸入時脈為25MHz時,量測結果顯示鎖相迴路輸出訊號的方均根抖動和峰值抖動分別為15.66ps和110ps,消耗功率為20mW。

This thesis describes the design of a transmitter for a high-speed serial digital display interface that uses transition minimized differential signaling (TMDS) to send data to the monitor. The transmitter consists of a multi-phase phase-locked loop (PLL), a 10-to-1 multiplexer and a data driver.
The multi-phase PLL with input frequency range from 25MHz to 165MHz can offer ten-phase clock output that has the same frequency with the input signal. It is composed of a phase-frequency detector (PFD), a charge pump (CP), a loop filter and a ten-phase voltage-controlled oscillator (VCO). The PLL can support several different video display modes from VGA (640×480) to UXGA (1600×1200). Ten different clock phases tapped from a five-stage differential ring oscillator to determine the bit time. They also control the transmitter multiplexing. Finally, the data driver outputs serial data steam.
The transmitter is implemented in a 1P4M CMOS process and the supply voltage is 3.3V. The measured rms and peak-to-peak jitters of the 25MHz output clock of the PLL are 15.66ps and 110ps, respectively, and power consumption is 20 mW.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation…………………………………………………………...…………1
1.2 Digital Video Interface….……………………………………………………...2
1.3 Organization…………………………………………………………………....5
CHAPTER 2 INTERCONNECT DESIGN 7
2.1 Introduction…………………………………………………………………….7
2.2 Basic Link Design………………………………..…………………………….7
2.3 Noise Consideration……………………………………………………….…...9
2.3.1 Crosstalk………….……………………………………………………...9
2.3.2 Self-induced power supply noise………….……………………………11
2.3.2 Intersymbol Interference………………………………………………..11
2.3.4 Random Noise…………………………………………………………..13
2.4 Signaling Circuit………………………………..…………………………….14
2.4.1 Transmitter Design……………………………………………………..14
2.4.2 Terminations…………………………………………………………….16
CHAPTER 3 PHASED LOCKED LOOP 19
3.1 Introduction…………………………………………………………………...19
3.2 PLL Architecture…………..……………………………………….…………19
3.3 Circuit Implementation……………………………………….………………20
3.3.1 Phase Frequency Detector……………………………………………...20
3.3.2 Charge Pump…………………………………………………….……...23
3.3.3 Voltage Control Oscillator……………………………………….….….25
3.4 PLL Linear Model……...………………………………………………..……30
3.5 PLL Noise Analysis…………………………………………………………..32
3.6 System Response and Stability...……………………………………………..35
CHAPTER 4 TRANSMITTER 39
4.1 Transmitter Architecture……………………………………………………...39
4.2 10:1 Multiplexer……..……………………………………………………….40
4.3 Data Driver…………..……………………………………………………….41
4.4 Swing Control Circuit…..…………………………………………………….43
4.5 A Transmitter with Transmit Signal Pre-Emphasis………………….….…….44 4.4 Simulation Result…...…..…………………………………………………….47
CHAPTER 5 EXPERIMENTAL RESULT 51
5.1 Transmitter Without Transmit Signal Pre-Emphasis……………………...….51
5.1.1 PLL Experimental Result…..…………………………………………...53
5.1.2 Transmitter Experimental Result…..…………………………………...56
5.2 Transmitter With Transmit Signal Pre-Emphasis…..……………………...….58
CHAPTER 6 CONCLUSION AND FUTURE WORK 61
6.1 Conclusion……………………………………………………………………61
6.2 Future Work……………………………………………………..……………62
REFERENCES………………………………..……………………...…63
VITA…………………………………..…………….……………………67

REFERENCES
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