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研究生:鄭之瑜
研究生(外文):Chih-Yu, Cheng
論文名稱:適用於ITU-TJ.83B纜線數據機的前置錯誤更正解碼器
論文名稱(外文):A FEC Decoder for ITU-T J.83B Cable Modem Application
指導教授:李鎮宜
指導教授(外文):Chen-Yi, Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:71
中文關鍵詞:纜線數據機前置錯誤更正解碼器
外文關鍵詞:Cable ModemForward Error CorrectionTrellis Coded ModulationViterbi algorithmReed-Solomon DecoderBerlekamp-Massey algorithmFPGA
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數位訊號傳輸在通訊系統中逐漸佔有重要的地位,隨著資料量日益增加以及通訊環境複雜性升高,Forward Error Correction (FEC) 已成為通訊系統中必要的功能。在這篇論文中,我們針對ITU-T J.83B Cable Modem規格書中的FEC做討論。首先使用C程式完成整個系統的模擬,包含FEC Encoder和FEC Decoder;接下來用Verilog-HDL code完成FEC Decoder的部分,其中包括Trellis decoder,De-radomizer,De-interleaver,Reed-Solomon decoder的電路設計,且可符合Cable Modem中64-QAM與256-QAM兩種不同的模式,再使用0.35mm SPQM Avant! Cell library進行合成,並模擬無誤;最後以Xilinx的FPGA來驗證整個J.83B FEC Decoder的功能是否正確。
除了完整實現整個ITU J.83B FEC Decoder的硬體架構外,我們也針對了FEC Decoder提出了一些新的設計架構。在Trellis decoder中,對Viterbi decoder的trace back部分做了兩種不同的改進,第一種架構可以提升trace back的速度,第二種架構則能降低trace back所消耗的功率。而在De-interleaver中,我們提出了一種可以有效減少記憶體數量以及簡化位址產生器的方法。另外,我們使用了一個可以參數化的RS decoder HDL code產生器,輸入所需的參數即可得到RS decoder的Verilog code,其中所採用的解碼方式為Berlekamp-Massey algorithm,並且它提出了十分節省硬體的decomposed架構;但是因為在ITU J.83B中定義的RS decoder與一般有些許不同,因此我們必須對產生的RS decoder做修正才能使用。
在我們提出的架構下,以上述的Cell library合成,需要約44.2K的邏輯閘數目,以及8K*7 bit的single port記憶體。而最後以Xilinx XVC2000E FPGA測試,速度可達到12.5Msymbol/s。

Digital signal transmission becomes dominant in data communication system these years. With the large amount of data quantity and complex transmission environment, Forward Error Correction (FEC) is getting important. This thesis focuses on the FEC decoder in ITU-T J.83B Cable Modem Network recommendation. At first, the function of FEC encoder and FEC decoder are simulated with C program, then we complete the hardware architecture, which contains Trellis decoder, De-randomizer, De-interleaver, and Reed-Solomon decoder. After synthesized by 0.35mm SPQM Avant! Cell library, our FEC decoder is also realized with Xilinx FPGA.
In this thesis, some new hardware architectures are proposed for FEC decoder. In Trellis decoder, there are two proposals for trace-back module in Viterbi decoder. One can accelerate the trace back and the other can reduce the power consumption. Also, there is a novel method for De-interleaver to lessen the number of registers and simplify the calculation of memory addresses. Further, a parameterized Reed-Solomon decoder is employed in FEC decoder. It is easy to be programmed for different application and reduce the hardware complexity efficiently. However, the Reed-Solomon decoder needs to be modified because of the slight difference with the ordinary Reed-Solomon decoder.
With the proposed architecture, the FEC decoder requires 44.2K gate counts with 0.35 Avanti! Cell library, and an 8K*7 bit RAM. And it can work at 12.5MHz with Xilinx XCV2000E FPGA device.

Chapter 1 Introduction
1-1 Introduction of ITU-T J.83B FEC Codec
1-2 Research Motivation
1-3 Organization of this thesis
Chapter 2 Algorithm of FEC Encoder
2-1 FEC encoder
2-2 Reed-Solomon encoder
2-2-1 BRIEF INTRODUCTION OF RS CODING
2-2-2 RS ENCODER IN ITU-T J.83
2-3 Interleaver
2-4 Randomizer
2-5 Trellis coded modulation (TCM)
2-5-1 BRIEF INTRODUCTION OF TCM
2-5-2 TCM IN ITU-T J.83
Chapter 3 Algorithm and architecture of FEC Decoder
3-1 Trellis coded modulation
3-1-1 VITERBI ALGORITHM
3-1-2 PUNCTURED CONVOLUTIONAL CODE
3-1-3 DECODING TRELLIS CODE
3-2 Synchronization and de-randomizer
3-2-1 FRAME SYNCHRONIZATION
3-2-2 DE-RANDOMIZER
3-3 De-interleaving
3-3-1 DE-INTERLEAVER FOR 64-QAM
3-3-2 DE-INTERLEAVER FOR 256-QAM
3-4 Reed-Solomon decoder
3-4-1 SYNDROME CALCULATOR
3-4-2 KEY EQUATION SOLVER
3-4-3 CHIEN SEARCH
3-4-4 ERROR VALUE EVALUATOR
3-4-5 DESIGN SUMMARY
Chapter 4 System Implementation and Simulation Result
4-1 System design flow
4-2 FPGA integration and simulation
4-3 Simulation results and comparisons
Chapter 5 Conclusion and Future Work
5-1 Conclusion
5-2 Future works
Reference

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