跳到主要內容

臺灣博碩士論文加值系統

(54.225.48.56) 您好!臺灣時間:2022/01/19 22:51
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:王經楷
研究生(外文):Keng-Khai Ong
論文名稱:適用於多種影像壓縮標準的高產出率及低功率算數編解碼器設計
論文名稱(外文):A High-throughput and Low-power Arithmetic CODEC Design for Multiple Image Compression Standards
指導教授:李鎮宜
指導教授(外文):Chen-Yi Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:102
中文關鍵詞:算數編碼高產出率低功率影像壓縮JPEG-2000 JPEG JBIG JBIG2動態關閉時脈MQ coder QM coder
外文關鍵詞:Arithmetic CodingHigh throughputLow powerImage CompressionJPEG-2000 JPEG JBIG JBIG2Dynamic gated clockMQ coder QM coder
相關次數:
  • 被引用被引用:0
  • 點閱點閱:331
  • 評分評分:
  • 下載下載:42
  • 收藏至我的研究室書目清單書目收藏:1
算數編碼在過去幾年來有越來越被重視的趨勢。許多未來的國際標準都把算數編碼列為關鍵元件。因此,其相關的硬體研究也就越顯重要。在本論文中,我們提出了一個硬體架構同時適用在JPEG, JBIG, JPEG-2000及JBIG2所使用的MQ及QM編碼器。他成功的將架構管線化為三個階段並達到每個週期能夠編碼或解碼出一個符號的效率。在低功率的考量上,使用了硬體共享及動態關閉時脈的機制。我們同時提出了使用動態關閉時脈技術的系統化設計流程,從硬體描述語言的指導原則到合成與佈局時的時脈樹產生技術。使用我們的架構,JPEG-2000的算數編解碼器的編碼及解碼產出率將可以分別達到200Msymbol/sec及182Msymbol/sec。其邏輯閘數僅有10K且在100Mhz下也僅消耗低於20mA的電流。至於支援多標準的編解碼器,其編碼及解碼的產出率分別為133Msymbol/sec及125Msymbol/sec。其邏輯閘數約為14K。因此,我們的設計擁有符合多標準,高產出率,低功率,低成本的特性,能夠付合即時及可攜性應用上的需求。

Arithmetic coding has become more and more popular in recent years. Many future international standard adopt arithmetic coding as its essential element. Its related hardware architecture research is in great demand. In this thesis, we proposed an architecture support both MQ and QM coder that adopt in JPEG, JBIG, JPEG-2000 and JBIG2. It successfully pipelines the design into three stages that can encode and decode a symbol in each cycle. For low power consideration, hardware sharing and dynamic gated clock mechanism is exploited in our design. We also proposed a systematic way to exploit dynamic gated clock mechanism into a system from RTL coding guideline, synthesis constraint to APR clock tree generation. Using our proposed architecture, encoding and decoding throughput rate of arithmetic codec for JPEG-2000 is up to 200Msymbol/sec and 182Msymbol/sec respectively while only cost 10K gate count and consume less than 20mA@100Mhz. As for multi-standard codec, encode and decode throughput rate runs up to 133Msymbol/sec and 125Msymbol/sec respectively. It costs 14K gate count. As a result, our design adopted multi-standard, high-throughput, low power and low cost characteristic that can be used for real-time and portable applications.

Chapter 1. Introduction
1.1 Motivation
1.2 Introduction to Arithmetic Code
1.3 Implementation and Mutation of AC
1.3.1 Integer Implementation of Arithmetic Coding
1.3.2 Context-based Arithmetic Coding
1.3.3 Multiplication Free Arithmetic Coding
1.4 Reviews of Arithmetic CODEC Design
1.4.1 Bottlenecks of Arithmetic Coding
1.4.2 Reviews of Arithmetic CODEC Architecture Design
1.4.3 Summary
1.5 Organization of this thesis
Chapter 2. Arithmetic Coding in Multiple Standards
2.1 MQ-Coder (JPEG-2000, JBIG2)
2.1.1 Encoding
2.1.2 Generation of Tag
2.1.3 Decoding
2.2 QM-Coder (JPEG, JBIG2)
2.1 Generation of context
2.2.2 Probability estimation table
2.2.3 MPS and LPS definition
2.2.4 Bit-stuffing and carry propagation handling
2.2.5 Generation of Tag
2.3 Summary
2.4 Shape Coding of MPEG-4
Chapter 3. Pipeline Arithmetic Coding Algorithm
3.1 Pipeline Arithmetic Encoding Flow
3.1.1 Overview
3.1.2 Interval Maintainer
3.1.3 Bit-Stuffing Handler
3.1.4 Output FIFO
3.2 Pipeline Arithmetic Decoding Flow
3.2.1 Overview
3.2.2 Embedded Stuffing Bit Carry Recover Input FIFO
3.2.3 Parallel and predictive Bitstream Organizer
3.2.4 Tag Maintainer
Chapter 4. Pipelined Arithmetic CODEC Architecture
4.1 Pipeline Arithmetic Encoder Architecture
4.1.1 Interval Maintainer
4.1.2 Bit Stuffing Handler
4.1.3 Output FIFO
4.2 Pipeline Arithmetic Decoder Architecture
4.2.1 Input FIFO
4.2.2 Bitstream Organizer
4.2.3 Tag Maintainer
4.3 Pipeline Arithmetic CODEC Architecture
4.4 Architecture Comparison and Analysis
4.5 Critical Path Analysis and Timing Optimization
4.6 Low Power Consideration
4.6.1 Digital System Power Analysis
4.6.2 Compression System Power Optimization Mechanism
4.6.3 Power Saving Strategies
4.6.3.1 Hardware Sharing Power Reduction (Reduce C)
4.6.3.2 Dynamic Power Gating and Optimization (Reduce α)
4.6.3.3 Clock Tree Buffers and Flip-Flops Power Minimization (Reduce α)
4.6.3.4 High throughput (Reduce V and F)
4.7 Summary
Chapter 5. Design and Implementation Methodology
5.1 Gated clock signal and system operating edge
5.2 Dynamic gated clock mechanism
5.2.1 Guideline to design gated clock system
5.2.2 Design flow overview
5.2.3 Problem cause by gated clock mechanism
5.3 Gated Clock Tree Generation
Chapter 6. Chip Implementation and Comparison
6.1 CODEC Chip implementation
6.2 Testing Circuits and Strategies
6.2.1 Embedded Run Time Hardware Monitor
6.2.2 Dynamic Power Analyzer
6.2.3 Pull out clock tree leaf pin
6.3 Chip Summary and Features
6.4 Testing vector
6.5 Full function
6.6 Comparison
Chapter 7. Conclusion and future work
7.1 Conclusions
7.2 Future Work
Bibliography
Appendix A. Throughput Requirement
Appendix B. Chip Pin Lists
About the Author

[1] CCITT Recommendation T.81, “Digital Compression and Coding of Continuous-tone Still Images,” 1992.
[2] ISO/IEC FCD15444-1, “JPEG2000 Part I Final Committee Draft Version 1.0”, March 2000.
[3] ISO/IEC 11172-2, “Coding of moving pictures and associated audio for digital storage media up to 1.5Mbit/s,” 1992.
[4] ISO/IEC 13818-2, “Generic coding of moving pictures and associated audio information: Video,” May 1994.
[5] ISO, MPEG-4 Video Verification Model version 17.0, ISO/IEC JTC1/SC29/WG11 N3515, Beijing, Jul. 2000.
[6] G.G. Langdon, “An introduction to arithmetic coding,” in IBM Journal of Research and Development, Vol. 28, no. 2, pp. 135-149, 1984.
[7] I.H. Witten, R.M. Neal, J.G. Cleary, “Arithmetic Coding for Data Compression,” in Communications of the ACM, vol. 30, no. 6, pp. 520-540, June 1987.
[8] D.A. Huffman, “A method for the construction of minimum-redundancy codes,” in Proc. IRE, Vol.40, pp.1098-1011, Sept. 1952.
[9] C.E. Shannon, “A mathematical theory of communication,” in Bell System Technical Journal, Vol. 27, pp. 379-423, 623-656, 1948.
[10] ISO/IEC International Standard 14492-FCD: Information technology - coded representation of picture and audio information — lossy/lossless coding of bi-level images, Jul. 1999.
[11] ITU-T Q.15/SG16, “H.26L test model long term number 9 (TML-9) draft 0,” Doc. VCEG-N81 D1, Dec 2001.
[12] K. Saywood, “Introduction to Data Compression 2nd edition,” Chapter 4, pp. 77-116, 2000.
[13] Yew-San Lee, Bai-Jue Shieh, Chen-Yi Lee, “A generalized prediction method for modified memory-based high throughput VLC decoder design,” in IEEE Trans. on Circuit and Systems II: Analog and Digital Signal Processing, vol. 46 no. 6, pp.742-754, Jun. 1999.
[14] Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee, “A new approach of group-based VLC codec system with full table programmability,” in IEEE Trans. on Circuit and Systems for Video Technology, vol. 11, no. 2, pp. 210-221, Feb. 2001.
[15] Ellis Horowitz, Sartaj Sahni, Susan Anderson-Freed, “Fundamentals of Data Structures in C”, pp. 228-231, 1993.
[16] J. Rissanen, K.M. Mohiuddin, “A multiplication-free multialphabet arithmetic code,” in IEEE Trans. on Communications, vol. 37, no. 2, pp. 93-98, Feb. 1989.
[17] Shaw-Min Lei, “Efficient multiplication-free arithmetic codes,” in IEEE Trans. on Communications, vol. 43, no. 12, pp. 2950-2958, Dec 1995.
[18] Bin Fu, K.K. Parhi, “Generalized multiplication-free arithmetic codes,” in IEEE Trans. on Communications, vol. 45, no. 5, pp. 497-501, May 1997.
[19] Linh Huynh, “Multiplication and division free adaptive arithmetic coding techniques for bi-level images,” in Data Compression Conference, 1994. DCC `94. Proceedings, pp.264-273, 1994.
[20] K.K. Parhi, “VLSI Digital Signal Processing Systems,” Chapter 2, pp. 43-61, 1999.
[21] David Taubman, Erik Ordentlich, Marcelo Weinberger, Gadiel Seroussi, Ikuro Ueno, Fumitaka Ono, “Embedded block coding in JPEG2000,” in Image Processing, 2000, Proceedings, 2000 International Conference, vol. 2, pp. 33-36, 2000.
[22] Gilberto I. Sada, Brayn Usevitch, “A practical binary ‘Bit Stuffing” method for multiplierless arithmetic encoders,” in Circuit and Systems, 2000. 42nd Midwest Symposium, vol. 2, pp. 1005-1007, 2000.
[23] J. Jiang, S. Jones, “Parallel design of arithmetic coding,” in Computers and Digital Techniques, IEE Proceedings, vol. 141, issue 6, pp. 327-333, Nov. 1994.
[24] Po Tong, Peng Ang, “A JBIG arithmetic coder-decoder chip,” in ASIC Conference and Exhibit, 1992, Proceedings of Fifth Annual IEEE International, pp. 189-192, 1992.
[25] Masaya TARUI, Masaru OSHITA, Takao ONOYE, Isao SHIRAKAWA, “High-speed implementation of JBIG arithmetic coder,” in TENCON 99, Proceedings of the IEEE Region 10 Conference, vol. 2, pp. 1291-1294, 1999.
[26] Hong-Hui Chen, Chung-Jr Lian, Kuan-Fu Chen, Liang-Gee Chen, “Context-based adaptive arithmetic encoder design for JPEG2000,” in Proceedings of Taiwan VLSI Design/CAD Symposium 2001, Section C1-10, Aug. 2001.
[27] M. Berekovic, K. Jacob, P. Pirsch, “Architecture of a hardware module for MPEG-4 shape decoding,” in Circuit and System, 1999, ISCAS ’99. Proceedings of 1999 IEEE International Symposium on, vol. 1, pp. 157-160, 1999.
[28] Danian Gong, Yun He, “An efficient architecture for real-time content-based arithmetic coding,” in Circuit and System, 2000, Proceedings, ISCAS 2000, Geneva, The 2000 IEEE International Symposium on, vol. 3, pp. 515-518, 2000.
[29] Horng-Yeong Lee, Leu-Shing Lan, Ming-Hwa Sheu, Chien-Hsing We, “A parallel architecture for arithmetic coding and its VLSI implementation,” in Circuit and System, 1996, IEEE 39th Midwest Symposium on, vol. 3, pp. 1309-1312, 1996.
[30] Gennady Feygin, Patrick Glenn Gulak, Paul Chow, “Architectural advances in the VLSI implementation of arithmetic coding for binary image compression,” in Data Compression Conference, 1994, DCC `94, Proceedings, pp. 254-263, 1994.
[31] Shiann Rong Kuang, Jer Min Jou, Ren Der Chen, Yeu Horng Shiau, “Dynamic pipeline design of an adaptive binary arithmetic coder,” in IEEE Trans. on Circuit and System II: Analog and Digital Signal Processing, vol. 48, issue 9, pp. 813-825, Sept. 2001.
[32] Shiann-Rong Kuang, Jer-Min Jou, Yuh-Lin Chen, “The design of an adaptive on-line binary arithmetic-coding chip,” in IEEE Trans. on Circuit and System I: Fundamental Theory and Applications, vol. 45, issue 7, pp. 693-706, Jul. 1998.
[33] ISO/IEC FCD15444-1, Annex C
[34] W.B. Pennebaker, J.L. Mitchell, G.G. Langdon, and R.B. Arps, “An overview of the basic principles of the q-coder adaptive binary arithmetic coders,” IBM Journal of Research and Develop, vol. 32, pp. 717-726, Nov. 1988.
[35] ISO/IEC International Standard 11544: ITU-T Rec. T.82, Coded Representation of Picture and Audio Information-Progressive Bi-level Image Compression, 1993.
[36] W. Pennebaker, J. Mitchell, G. Langdon and R. Arps, “An overview of the basic principles of the Q-coder adaptive binary arithmetic coder,” in IBM Journal Research Develop, vol. 36, pp. 717-726, Nov. 1998.
[37] S. Mallat, “A theory for multiresolution signal decomposition: the wavelet representation,” in IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. 11, no. 7, Jul. 1989.
[38] C.S. Wallace, “A suggestion for a fast multiplier,” in IEEE Trans. on Electronic Computers, EC-13(1), Feb. 1964, pp.14-17.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top