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研究生:宋承翰
研究生(外文):Cheng-Han Sung
論文名稱:具可延展之快速傅利葉轉換模組之設計與製作
論文名稱(外文):Design and Implementation of A Scalable Fast Fourier Transform Core
指導教授:任建葳任建葳引用關係
指導教授(外文):Chein-Wei Jen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:89
中文關鍵詞:快速複利葉轉換
外文關鍵詞:FFT
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就現存所採用OFDM技術的通訊協定的速度需求來看,FFT模組需要採用兩套的運算單元在single PE的架構之下.兩套運算單元會導致四筆資料同時自記憶體讀取的需求.採用多埠的記憶體會導致不必要的功率消耗以及硬體面積上的浪費.在我們的論文中,我們推導了可將原先多埠記憶體的需求轉換成多個單埠記憶體需求的不衝突資料格式來達到低功率消耗和低面積成本的需求.除了推導不衝突的資料格式之外,我們也從硬體的角度提出了一個描述不衝突資料格式的方程式.藉由使用我們的方程式,我們可以實現功能而不會有不必要的硬體花費.一個成功地將多埠記憶體轉換成多個單埠記憶體需要兩件事.一是推導不衝突的資料格式,另一是一個適合不衝突資料格式的位置產生器.在我們的論文中,我們提出了一套可以藉由計數器的值來產生四筆位置的位置產生機置.除了固定點數的位置需求之外,我們也發展了具言展性的位置產生機置.使用唯讀記憶體來標示何時以及何地來執行複數乘法是一種不實際的方法,於是我們提出了一套機置來預測複數乘法所發生的位置以及對應的數值來取代原先消耗大量面積的唯讀記憶體.不同的速度需求會導致不同的記憶體埠數的不同.就不同的速度而言,我們提出了一套方法來處理記憶體埠數為二的冪次的情形.在我們的方法中,我們只需要一套位置產生器來處理埠數為二的冪次的速度需求而不用修改先前IRDA的位置產生器的概念.傅利業轉換是一個消耗大量功率的產品,因此我們需要在設計初期來高階估計功率消耗的情形.在我們的論文中,我們提出了一套以記憶體分割為焦點的高階功率模型來描述功率消耗.從我們的功率模型來看,我們可以得知一個多埠記憶體的功率消耗可以藉由被取代成多個單埠記憶體來戲劇性地被減少.

For the speed requirement of existing communication standards that adopt OFDM technique, we should employee two processing elements in single PE architecture in FFT module, which will induce the requirement of accessing four data in the same cycle from the memory. Employing multiple-port memory will cause redundant power dissipation consume a lot of silicon area. In our thesis, we derive non-conflicting data format that can be adopted to replace single multiple-port memory to multiple single-port memories to achieve the purpose of low area cost and low power dissipation. Besides deriving non-conflicting data format, we also propose an equation to descript the non-conflicting data format from the hardware points of view. By using our equation, we can implement the function without redundant hardware cost. The successful implement for translating single multiple-port memory to multiple single-port memories will require two things. One is non-conflicting data format, the other is a suitable address generator. In our thesis, we propose our address-generating scheme that can generate four addresses easily from simple counter value. Besides the requirement of addresses of fixed length FFT, we also develop scalable-length ability in our address-generating scheme. Using ROM to indicate when and where we perform twiddle factor is not a feasible method, thus we propose a mechanism that can predict the position and the value of twiddle factor to replace a lot of silicon of ROM. Different speed requirement will induce different number of port of memory. For the different speed requirement, we also propose a method that can handle the ports that is power of two. In our method, we only need one set of address generator to handle the speed requirement that needs power of two ports without modifying the concept of original address generator of IRDA. FFT module is a power-consuming product, hence we hope to high-level estimate the power dissipation in the beginning of design. In our thesis, we propose the high-level power model to describe the power dissipation that focus on the power dissipation of memory partition. From our power model, we can see that the power dissipation of single multiple-port memory can be reduced by replacing single multiple-port memory to multiple singe-port memories dramatically.

Chapter1. Introduction 7
1.1 Motivation 7
1.2 OFDM concept 7
1.3 The character of FFT in OFDM system 8
1.4 The FFT specification of the communication standards 10
1.5 The requirement of existing communication standards 10
1.6 Organization of the thesis 11
Chapter2. FFT design 13
2.1 Radix- FFT algorithm 14
2.1.1 Basic low radix algorithms 14
2.1.2 High radix algorithms 17
2.1.3 Other algorithms 19
2.2 Pipeline architecture 20
2.2.1 Shuffling strategy 20
2.2.2 Analysis of the architecture and the algorithms 23
2.2.3 Summary 24
2.3 Single PE architecture 25
2.3.1 Introduction 25
2.3.2 Other features of single PE architecture 26
2.3.3 Proposed IRDA concept 28
2.3.3.1 Non-conflicting data format 28
2.3.3.2 Equation for non-conflicting data format 37
2.3.4 Proposed scalable length FFT mechanism 38
2.3.5 Dynamically predict the position of twiddle factor 40
2.3.6 The concept of attached PE. 42
2.3.7 Summary 44
Chapter3. High-level power estimation model for FFT design 47
3.1 Extracting parameter 47
3.2 Proposed power model for single PE architecture 48
3.2.1 Algorithm inherent energy dissipation 48
3.2.2 Parameterize power dissipation of memory access 52
3.2.3 Parameterize power dissipation of register access 54
3.2.4 Macro power model 54
3.2.5 Summary 55
Chapter4. FFT/IFFT implementation for OFDM system 57
4.1 Low power issue 57
4.2 System architecture for 64/16 scalable length FFT design 58
4.3 Detail hardware requirement 64
4.4 Simulation results and analysis 65
4.5 Physical parameter 66
4.6 Summary 68
Chapter5. Conclusion 69
5.1 Conclusion remarks 69
REFERENCES 70
APPENDIX-A 73
APPENDIX-B 75
APPENDIX-C 77
APPENDIX-D 79

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