臺灣博碩士論文加值系統

現今多媒體應用越來越多樣化，可程式化的系統解決方案已成為主要的潮流，微處理器的架構及相關製程亦持續不斷提昇支援其所需的效能。但在功率消耗及價格訴求的考量下，強大的單一微處理器系統已不能滿足消費性產品的需求，特別是以電池供電的攜帶式設備。目前業界的解決方案是採取異質性平台(heterogeneous platform)，針對特定的應用群在微控制器旁添加額外的專屬輔助運算硬體，降低功率消耗及提升運算效率。
為加速產品的上市，採取事先設計及驗證的IP模組是一個有效的方案。但這些在先前計畫中被設計使用或是由third-party取得授權的硬體加速器模組通常都不太符合應用的需求；若開始著手設計新硬體，為了讓這個模組能重複被使用，也必須over-design。另外，要將此硬體模組加入系統中的HW/SW介面設計也是非常地煩瑣。鑑於以上考量，在此我們提出了一個加速運算之資料路徑的自動產生器(DSP Datapath Generator)。
使用者依據各自的應用指定不同的需求，此Datapath Generator則自動產生合適的資料路徑加速運算，使每一分投資的成本都能轉換成其最高的運算效率(computational efficiency)。大幅降低系統成本。另外，硬體部分我們採用業界標準AMBA AHB設計，可輕易地將我們自動產生的資料路徑整合進標準的計算平台中(如許多以ARM或PowerPC為核心之架構)。同時我們也提供自動產生的軟體驅動程式，有效解決一般系統設計師所必須面臨之煩瑣易錯的軟硬體介面問題。故我們提出的系統設計驗證流程之複雜度及所需的設計時間與一般純軟體系統的流程相去不遠，不會增加太多的負擔。

Embedded systems are trending toward programmable solutions to meet the time-to-market (TTM) requirements under unstable and changing standards. Technology improvement and architecture innovation drive the microprocessor performance continuously to sustain the complex multimedia applications. Novel products that support new standards require extremely high performance and cannot be power- and cost-efficient, especially for battery-powered and portable devices.
For years, the industry uses the heterogeneous approach to solve this problem, which attaches specific hardware accelerators to the host embedded processor. Pre-designed and verified IP modules can significantly reduce the development time. But the hardware IP seldom meets the application requirements. Even if the developer designs his/her accelerator from scratch, some over-design is required to make the hardware re-usable. Besides, the hardware/software interface is tedious and error-prone. These motivate a coprocessing datapath generator, which synthesizes a customized hardware accelerator with the interface modules.
We propose a DSP datapath generator in this thesis, which accepts the user-specified constraints to generate synthesizable Verilog code for an optimal hardware accelerator. For the specified speed requirement, the generator minimizes the number of concurrent functional units to reduce the cost. MIN (Multi-stage Interconnection Network) is adopted in this thesis as the interconnection template for large-scale accelerators to reduce the routing complexity and the silicon area in conventional MUX (multiplexor)-based architectures. The generated DSP datapath is wrapped in AMBA AHB with the auto-generated software driver, which facilitates the integration into standard platforms (e.g. several commercial ARM or PowerPC-powered hardware platforms). The generation of DCT, FFT, and DWT accelerators is available in the “Example” chapter with a complete accelerated JPEG encoder system.

Chapter 1 Introduction 1
1.1 SoC 1
1.2 Heterogeneous Computing Platform 3
1.3 CASCADE — Configurable and Scalable DSP Environment 5
1.4 Automatic Generation of Coprocessing Datapaths 8
1.5 Thesis Organization 10
Chapter 2 Related Works 13
2.1 HW/SW Codesign framework 13
2.1.1 COSYMA 16
2.1.2 Vulcan 17
2.2 Configurable Processor 18
2.2.1 Tensilica 18
2.2.2 ARM Coprocessor 21
2.2.3 ARC Core 22
Chapter 3 Architectures of the Coprocessing Datapath 25
3.1 Conventional Dataflow Architectures 25
3.2 SIU-based Architectures 31
3.2.1 Interconnection 32
3.2.2 Storage 37
3.2.3 Functional Units 40
3.2.4 AHB Wrapper 44
Chapter 4 Automatic Generation of the Coprocessing Datapath 57
4.1 High Level Synthesis and Our Proposed Architecture 57
4.2 Synthesis for MUX-based Architecture 62
4.2.1 Operation Scheduling (dfg2sch) 62
4.2.2 Stream Interface Converting (sch2siu) 68
4.2.3 Storage Content Allocation (siu2mp) 69
4.2.4 RTL Verilog Generation (mp2v) 74
4.3 MIN-based Architecture 74
4.3.1 Looping Algorithm 75
4.3.2 Modification in Cost Function 81
4.3.3 Output Conflict Problem 81
Chapter 5 Example 83
5.1 Baseline JPEG (Fast DCT kernel) 83
5.1.1 JPEG Encoder 84
5.1.2 Fast DCT 85
5.1.3 Results 88
5.1.4 Layout 91
5.2 FFT 92
5.2.1 Results 92
5.2.2 Layout 95
5.3 DWT 96
5.3.1 Results 97
5.3.2 Layout 100
5.4 Summary 101
Chapter 6 Conclusion and Future Work 105
6.1 Conclusion 105
6.2 Future work 106
Appendix A. Usage of Tool 109
Appendix B. File Formats 111
B.1 Data Flow Graph Format (.dfg) 112
B.2 Scheduled Format (.sch) 113
B.3 Stream Format (.siu) 115
B.4 Memory Port Format (.mp) 116
B.5 RTL Verilog file description 119
Appendix C. Declaration of Input/Output in <project_name>_fu.v and <project_name>_fu_syn.v 121
Appendix D. File Relationship 123

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