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研究生:蔡進成
研究生(外文):Chin-Cheng Tsai
論文名稱:鎖相迴路內建頻率飄移測量電路之研究
論文名稱(外文):On-Chip Jitter Measurement for Phase-Locked Loops
指導教授:李崇仁李崇仁引用關係
指導教授(外文):Prof. Chung-Len Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:西班牙文
論文頁數:34
中文關鍵詞:測試電路週期變動量
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鎖相迴路目前被廣泛地運用於許多高速電子系統中,可當時脈調整器,亦可當頻率同步器。輸出週期變動量對於鎖相迴路是一個非常重要的效能指標,它是輸出訊號與理想訊號時間差的變動,有可能領先,也有可能落後。過大的變動量在通訊系統中,可能造成資料的流失,在微處理機系統中,可能造成計算上的錯誤。關於輸出週期變動量測量問題,需要一個準確度高達微微秒的測試機器,才能求得較為準確的值,但是卻提高了測試成本。吾人則提出利用一簡單設計,內建於測試電路中,將時間差轉換成數位訊號,並由一連串的數位資料求得輸出週期變動量,如此由一般的邏輯測試機器就可以達到測量目的,大大地降低測試成本。未來在單晶片系統中亦可使用此內建電路設計量測輸出週期變動量。

Phase-Locked Loops (PLL) are used in many high-speed electronic systems. It can be employed as the clock recovery and the frequency synthesizer. Jitter is an important parameter in Phase-Locked Loops specifications. It can be defined as the deviations in a clock output transition from their ideal position. The deviation can either be leading or lagging the ideal position. In a communication system, a larger jitter affects data correctness. And in a microprocessor system, a larger jitter results in wrong computation. For the jitter measurement, we need a high-resolution (pico-second) instrument in the Automation Test Equipment (ATE) to acquire more accurate values. In the thesis, we propose a simple, built in the circuit under test, design to transfer timing difference to the digital signal. Jitter values are obtained from several digital words. As a result, a general logic ATE can do the jitter measurement and the cost of test can be reduced. This design can also be used in an SOC design to measure jitter.

Contents
Chinese abstract
English abstract
Acknowledgments
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Jitter in PLL Circuit
1.2 Review on Jitter-Related Research
1.2.1 System Modeling for PLL Noise Analysis
1.2.2 PLL Simulation Results with Noise Injection
1.2.3 Previous Work for Jitter Measurement
1.3 Outline of This Thesis
Chapter 2 Proposed Architecture for Jitter Measurement
2.1 Basic Idea
2.2 Time to Digital Converter Architecture
2.3 Testing Procedure
2.4 Detailled Design of Sub-Circuits
2.4.1 Delay Cell
2.4.2 Arbiter
2.4.3 Phase Detector
2.4.4 Control Logic
Chapter 3 Simulation Results
3.1 TDC Simulation Results
3.2 Simulation Results with CUT
Chapter 4 Conclusion
Reference

[1]Wajih Dalal & Daniel Rosenthal, “Measuing Jitter of High Speed Data Channels Using Under-sampling Techniques,” Proceedings IEEE International Test Conference, 1998, pp. 814
[2]Nelson Soo, “Jitter Measurement Techniques,” PERICOM Application Brief AB36, 11/30/00
[3]Keith A. Jenkins & James P. Eckhardt, “Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops,” IEEE Design and Test Computers, 2000, pp. 86-92
[4]Frank Herzel & Behzad Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,” IEEE Transactions on Circuits and Systems, Analog and Digital Signal Processing, VOL. 46, NO. 1,JAN. 1999
[5]Payam Heydari & Massoud Pedram, “Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops,” IEEE Custom Integrated Circuits Conference, 2000, pp. 443-446
[6]Heydari & Pedram, “Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective,” Computer Design, 2001, pp. 209-213
[7]Benoit R. Veillette & Gordon W. Roberts, “On-Chip Measurement of the Jitter Transfer of Charge-Pump Phase-Locked Loops,” Proceedings IEEE International Test Conference, 1997, pp. 776-785
[8]Stephen Sunter & Aubin Roy, “BIST for Phase-Locked Loops in Digital Applications,” Proceedings IEEE International Test Conference, 1999, pp. 532-540
[9]Nazmy Abaskharoun, Mohamed Hafed & Gordon W. Roberts, “Circuits for On-Chip Sub-Nanosecond Signal Capture and Timing Measurements,” Circuits and Systems, ISCAS 2001, pp. 174-177
[10]Antonio H. Chan & Gordon W. Roberts, “A Synthesizable, Fast and High-Resolution Timing Measurement Device Using A Component-Invariant Vernier Delay Line,” Proceedings IEEE International Test Conference, 2001, pp. 858-867
[11]C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes & Ralph K. Cavin, “A Sampling Technique and Its CMOS Implementation with 1Gb/s Bandwidth and 25 ps Resolution,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, Mar. 1994, pp.340-349
[12]Piotr Dudek, Stanislaw Szxzepanski & John V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Transactions on Solid-State Circuits, Vol. 35, No. 2, FEB. 2000, pp. 240-247
[13]Steven B. Kaplan, Alex F. Kirichenko, Oleg A. Mukhanov & Saad Sarwana, “A Prescaler Circuit for a Superconductive Time-to-Digital Converter,” IEEE Transactions on Applied Superconductivity, Vol. 11, No. 1, Mar. 2001, pp. 513-516
[14]Vadim Gutnik & Anantha Chandrakasan, “On-Chip Picosecond Time Measurement,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 52-53
[15]C.Y.Yang, G.K.Dehng, J.M.Hsu & S.I.Liu, “New dynamic flip-flops for high-speed dual modulus prescaler,” IEEE J. Solid State Circuits, vol. 33, Oct. 1998, pp. 1568-1571

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