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研究生:彭鴻鈞
研究生(外文):Hung-Chung Peng
論文名稱:用於WLAN802.11B射頻傳收器之多相位頻率產生器
論文名稱(外文):Multi-Phase Frequency Synthesizer Design for 802.11B Transceiver
指導教授:溫瓌岸
指導教授(外文):Kuei-Ann Wen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:103
中文關鍵詞:射頻傳收器頻率產生器
外文關鍵詞:TranscieverFrequency Synthesizer
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摘要
在射頻接收器的設計中,降頻混波器或升頻混波器是非常重要的構成要素。而諧波降頻混波器或諧波升頻混波器可以工作在一半的頻率。工作在二分之一頻率的混波器在射頻接收器的設計上可以避免壓控震盪器受到接收或發送的訊號影響。而較低的頻率使得頻率產生器設計上變的比較簡單。
但無可避免的,諧波降頻混波器或諧撥升頻混波器需要比較多的不同相位訊號。在這篇論文中,除了鎖相迴路外,也提出個一個可產生多相位的電路。這個多相位產生器是利用迴授的概念設計的,其所產生的訊號只有非常小的相位誤差。
多相位頻率產生器所採用的製程是用UMC.25 1P5M的製程,在本篇論文中將提供整個多相位頻率產生器的設計,分析,和最後的量測結果。

Abstract
Up conversion mixers and down conversion mixers are essential components in the transceiver design. Harmonic up conversion mixer or harmonic down conversion mixer can operate in half the local frequency. The harmonic mixer can reduce the noise from receiving signal or transmitting signal which influences the voltage control oscillator and frequency synthesizer will be easier to design in the half frequency.
While harmonic down conversion mixer or harmonic up conversion mixer needs multiple local signals. Except for the phase lock loop, a phase generator will be needed to support multiple phase and has been proposed in this thesis. This phase generator uses a feedback loop to generate less phase error.
The multi-phase frequency synthesizer is fabricated in UMC0.25 1P5M process. The circuit design, network analysis and measurement of the multi-phase frequency synthesizer will be described in this thesis.

摘要…………………………………………………… …. i
Abstract…………………………………………………….. ii
Contents……………………………………………………. vi
List of Figures……………………………………………… vii
List of Tables……………………………………………….. xii
Chapter 1. Introduction…………………………….. 1
Chapter 2. Architecture………………………………3
2.1 Phase generator……………………………....4
2.1.1 Delay component………………… 6
2.1.2 Phase detector……………………7
2.1.3 Delay controller………………..8
2.2 Phase lock loop…………………………………9
2.2.1 VCO…………………………………11
2.2.2 Prescaler…………………………12
2.2.3 Digital controller…………… 12
2.2.4 Phase frequency detector…… 13
2.2.5 Charge pump & Filter………… 13
Chapter 3. Analysis and simulation………………15
3.1 Phase generator……………………………… 15
3.1.1 Delay component…………………15
3.1.1.1 Phase delay……… 17
3.1.1.2 Delay phase range 20
3.1.1.3 Gain between two outputs 23
3.1.2 Phase detector………………… 23
3.1.3 Delay controller……………… 25
3.1.3.3 The first stage of the delay controller 26
3.1.3.2 The second stage of the delay controller 29
3.1.3.3 The third stage of the delay controller 31
3.1.3.4 Lock time…………………………………… 32
3.1.5 Simulation result of phase generator…………33
3.2 Phase lock loop………………………………… 36
3.2.1 VCO……………………………………36
3.2.1.1Phase noise……………36
3.2.1.2 Simulation result… 42
3.2.2 Prescaler …………………… 43
3.2.2.1 Eight-transistor TSPC D flip-flop………………… 44
3.2.2.2 Synchronous counter (divide-by-4/5)……………… 45
3.2.2.3 prescaler simulation…………………………… 46
3.2.3 PFD……………………………………48
3.2.4 Digital controller……………… 51
3.2.5 Charge pump and filter…………54Chapter 4. Layout and package…………………… 56
4.1 Phase generator …………………………………………. 56
4.2 VCO……………………………………………… 58
4.3 PLL………………………………………………… 60
Chapter 5. Measurement……………………………. 63
5.1 Phase generator………………………………… 63
5.2 VCO………………………………………………….65
5.3 Prescaler………………………………………… 73
5.4 PFD………………………………………………… 75
Chapter 6. Conclusions ……………………… 78
Chapter 7. Appendix one…………………………… 80
Reference…………………………………………………. 85
作者簡介…………………………………………………... 88

[1] Henrik O. Johansson “A Simple Precharged CMOS Phase Frequency Detector” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 295
[2]Byungsoo Chang, Joobae Park, and Wonchan Kim “ A 1.2 GHz COMS Dual-Mosulus Prescaler Using New Dynamic D-Type Flop-Flops” IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 31 NO.5, MAY 1996
[3] Jiren Yuan and Christer Sensson “ High-Speed CMOS Circuit Technique” IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 24 NO.1. FEBRUARY 1989
[4] N. H. E. Weste and K. Eshragrian, Principles of CMOS VLSI Design,
2nd ed. Reading, MA: Addison Wesley, 1993.
[5] Hamid R. Rategh, Student Member, IEEE, Hirad Samavati, Student Member, IEEE, and Thomas H. Lee, Member, IEEE” A CMOS Frequency Synthesizer with
an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver” IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 35, NO. 5, MAY 2000
[6] Francesco Svelto and Rinaldo Castello ”A bond-wire inductor-MOS varactor VCO tunable from 1.8 to 2.4 GHz.” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002 403
[7] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Proc. Custom Integrated Circuits Conf., May 2000, pp. 569—572.
[8] Ali Hajimiri, Student Member, IEEE, and Thomas H. Lee, Member, IEEE” A General Theory of Phase Noise in Electrical Oscillators” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998
[9]Byungsoo Chang, Joobae Park, and Wonchan Kim “ A 1.2 GHz COMS Dual-Mosulus Prescaler Using New Dynamic D-Type Flop-Flops” IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 31 NO.5, MAY 1996
[10] Jiren Yuan and Christer Sensson “ High-Speed CMOS Circuit Technique” IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 24 NO.1. FEBRUARY 1989
[11] J.Cranincks, M.Steyeart, H. Miyakawa,”A fully integrated spiral LC-CMOS VCO set to work with prescaler for GSM and DCS-1800 system”,in Proc.Custom integrated Circuits Conference, pp.403-406 May 1997
[12] Thomas H. Lee, Tamara I. Ahrens “ A1.4 GHz 3 mW CMOS LC Low Phase Noise VCO Using Tapped Bond Wire Inductances”
[13] F.Svelto, S.Deantoni and Rcastello “A 1mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO”
[14] Bram Ed Muer, M Borremans, M. Steyaert, and G. Li Pema” A2-GHz Low Phase Noise Integrated LC-VCO Set with Flicker Noise Upconversion Minimization” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000

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