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研究生:于文浩
研究生(外文):Wen-Hao Yu
論文名稱:高速輸出輸入介面之電路設計
論文名稱(外文):Circuit Design on High-Speed I/O Interfaces for Giga-Bit Applications
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou Ker
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:64
中文關鍵詞:輸出輸入介面電路低電壓差動訊號正向射極偶合邏輯電路射極偶合邏輯電路接收機發射機收發機
外文關鍵詞:I/O interfaceLVDSPECLECLreceivertransmittertransceiver
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摘要
近年來由於處理器運算速度越來越快,單位時間處理的資料量也日益增多,因此在電腦週邊設備資料的傳輸,及各式積體電路產品應用,這些都必須靠一個能大量傳送和接收資料量的介面電路來完成。在數十公里,甚至數百公里以上的長距離傳輸方面,可以利用光纖作為傳輸的工具,可是在幾十公尺甚至PCB上各晶片匯排流資料的傳輸,光纖傳輸就不切實際,因此必須靠纜線或是PCB上的傳輸線來收發資料。而若要達到高速且低功率的要求,則多採用差動低電壓模式來傳送訊號。
本論文研究的方向主要分為兩部份,第一部份是低壓差動訊號(LVDS)收發機的電路設計,它是利用0.25um CMOS的製程來實現,且操作在2.5V的電壓下,收發速度能達到超過1 Giga-bit/s的要求。
論文的第二部份則是正向射極耦合邏輯(PECL)發射機電路設計,它是利用操作在3.3V 0.35um CMOS 的製程來實現,與ECL 100K的邏輯電路相容,該電路之高電壓準位為2.35,低電壓準位為1.6V,其傳送速度能達到1 Giga-bit/s以上。
在這篇論文提到的兩種I/O介面的電路設計,都是點對點串列傳輸的形式,同時因為低功率及產生的雜訊少,具有廣泛之用途。

ABSTRACT
In recent year, the operation speed of processor becomes faster and faster, and could deal with huger data in unit time. Therefore, it needs a giga-bit transceiver interface circuit for the transmission between peripheral equipments of computer, and application at kinds of manufactures in life. Optical fiber transmission is adopted for long distance such as several miles, but it is impractical for bus transmission on PCB or local communication such as several meters long. The cable or transmission line on PCB is applied. For taking high speed and low power into account, the transceiver use differential low voltage to transmit signal.
The research of this thesis separate two sections. First the low voltage differential signal (LVDS) transceiver is introduced. It is implemented by 2.5V 0.25um CMOS process, and the data rate would exceed one gigabit per second.
The second section, positive emitter couple logic (PECL) transmitter is introduced. It operates under 3.3V power supply, and is implemented by 0.35um CMOS process. The transmission data rate could also exceed one gigabit per second.
The proposed I/O interface circuits are both point-to-point serial port transmission. Because of low power consumption and low noise, they are widely used for high data rate communication application.

CONTENTS
CHINESE ABSTRACT i
ENGLISH ABSTRACT iii
ACKNOWLEDGEMENTS v
CONTENTS vi
FIGURE CAPTIONS viii
CHAPTER 1 Introduction
1.1 Application of I/O Interface circuit 1
1.2 High-Speed and Low-Power Transceiver Circuit
Design 2
1.3 Thesis Organization 3
CHAPTER 2 Low Voltage Differential Signal (LVDS) Tansceiver
2.1 Introduction 4
2.2 Transceiver Architecture 4
2.3 Building Block of the Transmitter 6
2.3.1 Pre-Driver Circuit Description and Analysis 6
2.3.2 Driver Circuit Analysis 8
2.3.3 Termination for LVDS transceiver 9
2.3.4 Common-Mode Feedback Circuit 11
2.4 Building Block of the Receiver 12
2.4.1 Self-Biased Amplifier Circuit for Receiving Low- Voltage Differential Signal 13
2.4.2 Amplifier for Converting Full-Swing 15
2.5 Hspice Simulation of the LVDS Transceiver 15
2.5.1 The Transmitter Simulation 15
2.5.2 The Receiver Simulation 16
CHAPTER 3 Positive Emitter Coupled Logic (PECL) Transmitter
3.1 Introduction 18
3.2 Building Block of the Transmitter 20
3.2.1 The Driver Circuit 20
3.2.2 The Constant Current Source Circuit 23
3.2.3 The Replica Bias Circuit 24
3.2.4 The Pulse Current Circuit 25
3.3 Termination for PECL Transceiver 27
3.4 Hspice Simulation of the PECL transmitter 28
CHAPTER 4 Experimental Results of LVDS Tansceiver
4.1 The Measurement Results of Transmitter Circuit 30
4.2 The Measurement Results of Receiver Circuit 30
CHPATER 5 Conclusions and Future Works
5.1 Conclusions 32
5.2 Future Works 33
REFERENCES 34
FIGURES 36
VITA 65

REFERENCE
[1] Comparing bus solutions, Texas Instruments Inc., USA, 2000.
[2] Logic selection guide first half 2002, Texas Instruments Inc., USA, 2000.
[3] Advanced bus interface logic selection guide, Texas Instruments Inc., USA, 2000.
[4] Performance of LVDS with different cables, Texas Instruments Inc., USA, 2000.
[5] IEEE standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI), 1596.3 SCI-LVDS standard, IEEE Std. 1596.3-1996, 1994.
[6] W. J. Dally and J. W. Poulton, Digital systems sngineering, Cambridge, 1998.
[7] S. H. Hall, G. W. Hall, and J. A. McCall, High-speed digital system design: A handbook of interconnect theory and design practices, Wiley, 2000.
[8] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[9] A. Boni, A. Pierazzi, and D. Vecchi, “LVDS I/O interface for Gb/s-per-pin operation in 0.35-um CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
[10] R. Ludwig and P. Bretchko, RF circuit design: Theory and applications, Prentice Hall, 2000.
[11] B. Young, “Enhanced LVDS for signaling on the RapidIOTM interconnect architecture,” IEEE Conference on Electrical Performance of Electronic Packaging, 2000, pp.17-20.
[12] T. Gabara et al., “LVDS I/O buffers with a controlled reference circuit,” in Proc. of ASIC conf., Sep. 1997, pp. 311-315.
[13] B. A. Chapell et al., “Fast CMOS ECL receivers with 100-mv worst-case sensitivity,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 59-67, Feb. 1988.
[14] M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. Solid-State Circuits, vol. 26, no.2, pp.165-168, Feb. 1991.
[15] H. J. Schumacher, D. Jan, and S. Evert, “CMOS subnanosecond true-ECL output buffer,” IEEE J. Solid-State circuits, vol. 25, no. 1, pp. 150-154, Feb. 1990.
[16] Interfacing different logic with LVDS receivers, Texas Instruments Inc., USA, Sep. 2001.
[17] H. Djahanshahi, F. Hansen, and C. A. T. Salama, “ Gigabit/s ECL-compatible I/O interface in 0.35-um CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp.1074-1083, Aug. 1999.
[18] A. Boni, “1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-um CMOS,” IEEE J. Solid-State Circuits, vol. 26, no.6, pp.979-987, June 2001.
[19] B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2000.
[20] S. M. Sze, Physics of semiconductor devices, Wiley, 1981.
[21] H. J. Oguey and D. Aebischer, “CMOS current reference without resistance,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1132-1135, July 1997.
[22] Interfacing between LVPECL, LVDS, and CML, Texas Instruments Inc., USA, 2001.
[23] M. Horowitz, C. K. Yang, and S. Sidiropoulos, “High-speed electrical signaling: Overview and limitations,” IEEE Micro, vol. 18, no.1, pp. 12-24, Jan.-Feb. 1998.

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