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研究生:陳志熒
研究生(外文):Ying-Chih Chen
論文名稱:一個用於通道讀取之六位元每秒10億次取樣的類比數位轉換器
論文名稱(外文):A 6-bit 1GSample/s Analog-to-Digital Converter for Read Channel
指導教授:沈文仁吳錦川
指導教授(外文):Wen-Zen ShenJiin-Chuan Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:德文
論文頁數:56
中文關鍵詞:類比數位轉換器通道讀取快閃式類比數位轉換器
外文關鍵詞:A/D converteraverageflash adcread channel
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本篇論文描述一個六位元、每秒1000百萬次取樣用於通道讀取的全差動類比/數位轉換器。利用平均的技巧取代了以往自動歸零的方式,讓轉換器在自我校正的時候,也能夠持續轉換連續的輸入訊號而不中斷。平均的技巧是利用在空間域中輸入訊號跟偏移雜訊所看到的增益不同的優點來降低有效的偏移雜訊。文中,對平均的原理有詳細的分析和討論。此外,在本文中也提出了一個不同的終止技巧。為了減少功率的消耗,類比以及數位電路都用一個1.8伏特電源。預先放大器使用共模回溯的設計來提高在低電源下的輸入共模範圍。由模擬的結果顯示在470百萬赫茲及1000百萬赫茲的取樣頻率下,轉換器輸出的有效位數大於5.5。使用0.18微米單層複晶矽互補金氧半製程,消耗功率約為180毫瓦

A 6-bit 1-GSample/s fully differential CMOS flash analog-to-digital converter for read channel is described is this thesis. To achieve the goal of no-idle time for self-calibration of A/D converter, the conventional auto-zeroing scheme is replaced by averaging technique. Averaging technique takes the advantage of different gains seen by input signal and offset in spatial domain. The principle of averaging technique is analyzed and discussed in detail. And, a different termination technique is proposed in this thesis. In order to reduce the power consumption, a 1.8V power supply is for both analog and digital circuits. The pre-amplifier consists of CMFB circuit to improve the input common mode range at 1.8V. Simulation results show that the converter can achieve effective number of bit higher than 5.5 at the input frequency up to 470MHz and sampling frequency up to 1GHz. Using 0.18μm 1P6M CMOS process, the converter consumes 180mW at 1.8V when running at 1GHz.

Chapter 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 REVIEW OF OFFSET CANCELATION TECHNIQUE 4
2.1 Conventional Auto-zeroing Operation 5
2.2 Digital Offset Calibration 10
Chapter 3 AVERAGE 12
3.1 Principle of Averaging 12
3.2 Edge Effect 19
3.2.1 Terminated with an Equivalent Resistor 20
3.2.2 Terminated with Cyclic Network 22
3.2.3 Special Termination Approach 23
Chapter 4 CIRCUIT DESIGN and SIMULATION 26
4.1 Track-and-Hold 27
4.2 Pre-amplifier Array 29
4.3 Pipelining Latch 33
4.4 Digital Decoder 35
4.5 Clock Generator 36
Chapter 5 SIMULATION RESULTS 38
5.1 Fundamental Limitation of Differential Sampling Switch 38
5.2 Averaging Effect Simulation 45
5.3 Single Channel Simulation 47
5.4 Overall Simulation Results 49
Chapter 6 CONCLUSION and FUTURE WORK 52
6.1 Conclusion 52
6.2 Future Work 53
Bibliography 54

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