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研究生:石哲華
研究生(外文):Che-Hua Shih
論文名稱:硬體規格描述語言設計之錯誤診斷
論文名稱(外文):HDL Design Error Diagnosis
指導教授:周景揚周景揚引用關係
指導教授(外文):Jing-Yang Jou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:28
中文關鍵詞:硬體規格描述語言診斷
外文關鍵詞:HDLDiagnosis
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  • 下載下載:11
  • 收藏至我的研究室書目清單書目收藏:0
現今數位設計的複雜度越來越高,意味著當一個電路設計與所設計規格一旦不吻合之時,設計者想要在由硬體規格描述語言所設計之電路中,迅速找到錯誤位置也越來越困難。在這篇論文中,我們將提出一個對於自動錯誤診斷的有效方法,透過對此硬體規格語言程式所跑的模擬結果作分析,可診斷有多個錯誤的電路且只需要一組的測試向量。我們的方法主要就是要在維持一定有錯誤在我們所提出的錯誤候選者集合中的前提下,有效的刪去那些不可能為錯誤或是錯誤機率較低的候選者,藉此,來縮短除錯的時間。我們利用了許多實際電路來做實驗,根據實驗結果,我們確實有效地減少了錯誤候選者的數量,證實此方法的確可以得到不錯的功效。

The growing of the modern design complexity leads the design error diagnosis to be a challenge for designers when a mismatch occurs between an implementation in HDL and its design specification. In this thesis, we propose an efficient approach for design error diagnosis automatically. This approach can handle multiple errors occurred in a HDL design simultaneously with only one test case by analyzing the simulation outputs of the incorrect implementation. Furthermore, this approach reduces the error space by eliminating those statements that have no or lower possibility to become the error sources with retaining at least one error source in it. Hence, the effort spent on the debugging process can be reduced. Experiments are conducted over some real designs and the experimental results are very promising with obtaining set of smaller error space.

摘要 i
ABSTRACT ii
ACKNOWLEGEMENTS iii
CONTENTS iv
LIST OF TABLES vi
LIST OF FIGURES vii
Chapter 1 Introduction ……………………………………….….….. 1
Chapter 2 Preliminaries …………………………………………….. 5
2.1 Control Data Flow Graph …………………………… 5
2.2 Error Effect ………………………………………….. 7
2.3 A Previous Approach ………………………………... 8
Chapter 3 Our Approach ……………………………………………. 10
3.1 An Overview …………………….…………………... 10
3.2 Error Space Reduction Rules ………………………... 13
Chapter 4 Heuristic Selection …………………………………….. 20
4.1 Selection Situations …………………………………. 20
4.2 Cost Function ……………………………………….. 20
Chapter 5 Experimental Results ……………………………………. 24
Chapter 6 Conclusion ………………………………………………. 27
Reference ……………………………………………………………... 28

[1] S. -Y. Kuo, “Locating Logic Design Errors via Test Generation and Don’t-Care Propagation”, European Design Automation Conference, pp. 466-467, Sept. 1992.
[2] P. -Y. Chung, Y. -M. Wang, and I. N. Hajj, “Logic Design Error Diagnosis and Correction”, IEEE Transaction on VLSI System, vol.2, no.3, pp. 320-332, Sept. 1994.
[3] S. -Y. Huang, K. -T. Cheng, K. -C. Chen, and D. I. Cheng, “Error Tracer: A Fault Simulation-Based Approach to Design Error Diagnosis”, International Test Conference, pp. 974-981, Nov. 1997.
[4] A. Gupta and P. Ashar, “Fast Error Diagnosis for Combinational Verification”, The Thirteenth International Conference on VLSI Design, 2000, pp. 442-448, 2000.
[5] M. Fujita, “Methods for Automatic Design Error Correction in Sequential Circuits”, European Conference on Design Automation, pp. 76-80, 1993.
[6] S. -Y. Huang, K. -T. Cheng, K. -C. Chen, and J. -Y. Lu, “Fault-Simulation Based Design Error Diagnosis for Sequential Circuits”, Design Automation Conference, pp. 632-637, Jun. 1998.
[7] V. Boppana, I. Ghosh, R. Mukherjee, J. Jain, and M. Fujita, “Hierarchical Error Diagnosis Targeting RTL Circuits”, International Conference on VLSI Design, pp. 436-441, 2000.
[8] M. Khalil, Y. L. Traon, and C. Robach, “Towards an Automatic Diagnosis for High-level Design Validation”, International Test Conference, pp. 1010-1018, Oct. 1998.
[9] T. -Y. Jiang, “Functional Error Diagnosis for Designs in HDLs”, Master thesis, National Chiao Tung University, Jun. 2001.
[10] V. Boppana, and M. Fujita, “Modeling the Unknown! Towards Model Independent Fault and Error Diagnosis”, International Test Conference, Oct. 1998, pp. 1094-1101

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