臺灣博碩士論文加值系統

本論文描述一個3.3V，8位元，50M sample/s的類比至數位轉換器。其輸入電壓範圍為 0V~1.024V。整體架構採用子區間式(subranging)實現，因此不需要高增益頻寬的運算放大器(operational amplifier)。基本結構包含了一個外掛運算放大器作為取樣/保持電路(S/H)，約略比較器(coarse comparator)，精密比較器（fine comparator），參考電壓產生器（reference voltage generator），數位錯誤修正電路（digital error correction circuit），時脈產生器（clock generator）。電路操作上，首先由取樣/保持電路對輸入訊號作取樣，接下來則約略與精密比較器同時從取樣/保持電路輸出中取樣，其中31個約略比較器產生前5位元，15個精密比較器產生剩下的3位元，由8個精密比較器的結果控制數位錯誤修正電路來修正前5位元，最後得到八位元輸出。此類比數位轉換器使用TSMC 1P4M 0.35微米製程，並以混合訊號全客戶式佈局實現。由於金屬電容占大面積，因此所有電容皆以P型金氧半電晶體替代，所以晶片總面積只有1.5mm x 1.5mm。最後經由HSPICE模擬驗證，在50MHz取樣頻率下可達8位元解析度，在工作電壓3.3V下，總功率消耗約為64mW。

The thesis describes a 3.3V, 8-bit, 50M sample/s analog-to-digital converter. The input voltage range is 0V~1.024V. The ADC is implemented by the subranging architecture, so high gain-bandwidth operational amplifier (OP) is not needed. The architecture includes an external OP used to be a S/H, coarse comparators, fine comparators, reference voltage generator, digital error correction circuit, and clock generator. In the operation flow, the 5-bit MSBs are generated from 31 coarse comparators first, and the other 3 bits are generated from 15 fine comparators. Then, from the results of 8 fine comparators, the 5-bit MSBs are corrected by the digital error correction circuit to get final 8-bit output. The ADC is implemented by TSMC 1P4M 0.35um process and mixed-signal full custom layout is applied. The PMOS is used to be capacitor since the metal capacitor occupies larger area. So the chip area is only 1.5mm x 1.5mm. The ADC is verified to achieve 8-bit resolution at 50MHz sampling rate by HSPICE simulation. Under the condition of 3.3V power supply, the total power consumption is about 64mW.

ABSTRACT(CHINESE)………………………………………………………i
ABSTRACT(ENGLISH)…………………………………………………….ii
ACKNOWLEDGEMENT……………………………………………………. iii
CONTENTS……………………………………………………………....iv
FIGURE CAPTIONS.………………………………………………………vi
TABLE CAPTIONS………………………………………………….....vii
Chapter 1 Introduction
1.1 Motivation…………………………………………………………1
1.2 High Speed ADC Architecture………………………………….1
1.3 The Proposed 8-bit ADC…………………………………………4
1.4 Organization of The Thesis……………………………………5
Chapter 2 8-bit Subranging ADC Architecture
2.1 System Structure…………………………………………………6
2.2 Coarse and Fine ADC Block…………………………………….7
2.3 Transition Point Detector…………………………………….8
2.4 Encoder…………………………………………………………….9
2.5 Reference Voltage Generator…………………………………11
2.6 Digital Error Correction…………………………………….13
2.7 Clock Generator…………………………………………………14
2.8 Output Buffer……………………………………………………16
Chapter 3 Design of Comparator and Timing
3.1 Coarse Comparator………………………………………………17
3.2 Fine Comparator…………………………………………………20
3.3 Timing Description…………………………………………….26
Chapter 4 Layout Consideration
4.1 Transistor Matching……………………………………………28
4.2 Capacitor…………………………………………………………28
4.3 Resistor………………………………………………………….29
4.4 Floor Plan……………………………………………………….30
Chapter 5 Experiment Results
5.1 Test Setup……………………………………………………….31
5.2 Experiment Results…………………………………………….32
5.3 Summary……………………………………………………………36
Chapter 6 Conclusion and Future Works
6.1 Conclusion……………………………………………………….37
6.2 Future Works…………………………………………………….38
REFERENCES…………………………………………………………….40
FIGURE
TABLE
VITA

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